WOLA FFT Tabanli Kanallastirici Tasarimi

Enes Karav; Murvet Kirci; Oguzhan Kosar

doi:10.1109/SIU.2018.8404192

WOLA FFT Tabanli Kanallastirici Tasarimi

Enes Karav
, Murvet Kirci
, Oguzhan Kosar

Elektronik ve Hab.Müh.Bölümü

Istanbul Technical University

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

1 Atıf (Scopus)

Özet

The channelizer techniques that are common in use are examined in this thesis and weight overlap and add(WOLA) channelizer technique is designed in the MAT LAB Simulink platform and its advantages and disadvantages are examined in details. In the design phase, channelizer makes compatible for use with Xilinx FPGA family. VHSIC hardware identification language (VHDL) code of the channelizer that was designed on MATLAB Simulink is developed and synthesized on the Xilinx ISE platform. So, the resource utilization of the channelizer that was designed in the FPGA can be calculated.

Tercüme edilen katkı başlığı	Design of WOLA FFT based channelizer
Orijinal dil	Türkçe
Ana bilgisayar yayını başlığı	26th IEEE Signal Processing and Communications Applications Conference, SIU 2018
Yayınlayan	Institute of Electrical and Electronics Engineers Inc.
Sayfalar	1-4
Sayfa sayısı	4
ISBN (Elektronik)	9781538615010
DOI'lar	https://doi.org/10.1109/SIU.2018.8404192
Yayın durumu	Yayınlandı - 5 Tem 2018
Etkinlik	26th IEEE Signal Processing and Communications Applications Conference, SIU 2018 - Izmir, Türkiye Süre: 2 May 2018 → 5 May 2018

Yayın serisi

Adı	26th IEEE Signal Processing and Communications Applications Conference, SIU 2018

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	26th IEEE Signal Processing and Communications Applications Conference, SIU 2018
Ülke/Bölge	Türkiye
Şehir	Izmir
Periyot	2/05/18 → 5/05/18

Bibliyografik not

Publisher Copyright:
© 2018 IEEE.

Keywords

Channelizer
FPGA
MATLAB

Belgeye Erişim

10.1109/SIU.2018.8404192

Diğer Dosyalar ve Linkler

Link to publication in Scopus

Alıntı Yap

@inproceedings{0ff36af41a4142648d69257867f4acea,

title = "WOLA FFT Tabanli Kanallastirici Tasarimi",

abstract = "The channelizer techniques that are common in use are examined in this thesis and weight overlap and add(WOLA) channelizer technique is designed in the MAT LAB Simulink platform and its advantages and disadvantages are examined in details. In the design phase, channelizer makes compatible for use with Xilinx FPGA family. VHSIC hardware identification language (VHDL) code of the channelizer that was designed on MATLAB Simulink is developed and synthesized on the Xilinx ISE platform. So, the resource utilization of the channelizer that was designed in the FPGA can be calculated.",

keywords = "Channelizer, FPGA, MATLAB",

author = "Enes Karav and Murvet Kirci and Oguzhan Kosar",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 26th IEEE Signal Processing and Communications Applications Conference, SIU 2018 ; Conference date: 02-05-2018 Through 05-05-2018",

year = "2018",

month = jul,

day = "5",

doi = "10.1109/SIU.2018.8404192",

language = "T{\"u}rk{\c c}e",

series = "26th IEEE Signal Processing and Communications Applications Conference, SIU 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--4",

booktitle = "26th IEEE Signal Processing and Communications Applications Conference, SIU 2018",

address = "United States",

}

Karav, E, Kirci, M & Kosar, O 2018, WOLA FFT Tabanli Kanallastirici Tasarimi. in 26th IEEE Signal Processing and Communications Applications Conference, SIU 2018. 26th IEEE Signal Processing and Communications Applications Conference, SIU 2018, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 26th IEEE Signal Processing and Communications Applications Conference, SIU 2018, Izmir, Türkiye, 2/05/18. https://doi.org/10.1109/SIU.2018.8404192

WOLA FFT Tabanli Kanallastirici Tasarimi. / Karav, Enes; Kirci, Murvet; Kosar, Oguzhan.
26th IEEE Signal Processing and Communications Applications Conference, SIU 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4 (26th IEEE Signal Processing and Communications Applications Conference, SIU 2018).

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

TY - GEN

T1 - WOLA FFT Tabanli Kanallastirici Tasarimi

AU - Karav, Enes

AU - Kirci, Murvet

AU - Kosar, Oguzhan

PY - 2018/7/5

Y1 - 2018/7/5

N2 - The channelizer techniques that are common in use are examined in this thesis and weight overlap and add(WOLA) channelizer technique is designed in the MAT LAB Simulink platform and its advantages and disadvantages are examined in details. In the design phase, channelizer makes compatible for use with Xilinx FPGA family. VHSIC hardware identification language (VHDL) code of the channelizer that was designed on MATLAB Simulink is developed and synthesized on the Xilinx ISE platform. So, the resource utilization of the channelizer that was designed in the FPGA can be calculated.

AB - The channelizer techniques that are common in use are examined in this thesis and weight overlap and add(WOLA) channelizer technique is designed in the MAT LAB Simulink platform and its advantages and disadvantages are examined in details. In the design phase, channelizer makes compatible for use with Xilinx FPGA family. VHSIC hardware identification language (VHDL) code of the channelizer that was designed on MATLAB Simulink is developed and synthesized on the Xilinx ISE platform. So, the resource utilization of the channelizer that was designed in the FPGA can be calculated.

KW - Channelizer

KW - FPGA

KW - MATLAB

UR - https://www.scopus.com/pages/publications/85050792927

U2 - 10.1109/SIU.2018.8404192

DO - 10.1109/SIU.2018.8404192

M3 - Konferans katkısı

AN - SCOPUS:85050792927

T3 - 26th IEEE Signal Processing and Communications Applications Conference, SIU 2018

SP - 1

EP - 4

BT - 26th IEEE Signal Processing and Communications Applications Conference, SIU 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 26th IEEE Signal Processing and Communications Applications Conference, SIU 2018

Y2 - 2 May 2018 through 5 May 2018

ER -

WOLA FFT Tabanli Kanallastirici Tasarimi

Özet

Yayın serisi

???event.eventtypes.event.conference???

Bibliyografik not

Keywords

Belgeye Erişim

Diğer Dosyalar ve Linkler

Parmak izi

Alıntı Yap