RISC-V İşlemcisi Üzerinde Özel Komutlar ve LLVM Entegrasyonu ile SPHINCS+ PQC Algoritmasının Optimizasyonu

Mert Paşa Çukur; Ece Olcay Güneş

doi:10.1109/SIU61531.2024.10600793

RISC-V İşlemcisi Üzerinde Özel Komutlar ve LLVM Entegrasyonu ile SPHINCS+ PQC Algoritmasının Optimizasyonu

Mert Paşa Çukur
, Ece Olcay Güneş

Elektronik ve Hab.Müh.Bölümü

Istanbul Technical University

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

2 Atıf (Scopus)

Özet

With the emergence of quantum computers, traditional open key cryptographic schemes have faced an existential threat that necessitates the development of quantum resistant algorithms. Post Quantum Cryptography (PQC) has emerged as a solution that opposes this new cryptoanalytic evolution with hash based signature schemes such as SPHINCS+, known as one of the leading candidates by NIST. However, SPHINCS+ requires hardware acceleration for practical use. This study offers a method to accelerate the SPHINCS+ algorithm running in the RISC-V processor on the FPGA using the LLVM integration for custom instruction extension. Custom instructions have been developed for the SHA-256 operations, a fundamental component of SPHINCS+, resulting in a 5.09x acceleration of the algorithm.

Tercüme edilen katkı başlığı	Optimization of the SPHINCS+ PQC Algorithm with Custom Instructions and LLVM Integration on a RISC-V Processor
Orijinal dil	Türkçe
Ana bilgisayar yayını başlığı	32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings
Yayınlayan	Institute of Electrical and Electronics Engineers Inc.
ISBN (Elektronik)	9798350388961
DOI'lar	https://doi.org/10.1109/SIU61531.2024.10600793
Yayın durumu	Yayınlandı - 2024
Etkinlik	32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Mersin, Türkiye Süre: 15 May 2024 → 18 May 2024

Yayın serisi

Adı	32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024
Ülke/Bölge	Türkiye
Şehir	Mersin
Periyot	15/05/24 → 18/05/24

Bibliyografik not

Publisher Copyright:
© 2024 IEEE.

Keywords

LLVM
Post Quantum Cryptography (PQC)
RISC-V
SHA-256 optimization
SPHINCS+
custom instructions
hardware acceleration
vector instructions

Belgeye Erişim

10.1109/SIU61531.2024.10600793

Diğer Dosyalar ve Linkler

Link to publication in Scopus

Alıntı Yap

Çukur, M. P., & Güneş, E. O. (2024). RISC-V İşlemcisi Üzerinde Özel Komutlar ve LLVM Entegrasyonu ile SPHINCS+ PQC Algoritmasının Optimizasyonu. In 32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings (32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SIU61531.2024.10600793

Çukur, Mert Paşa ; Güneş, Ece Olcay. / RISC-V İşlemcisi Üzerinde Özel Komutlar ve LLVM Entegrasyonu ile SPHINCS+ PQC Algoritmasının Optimizasyonu. 32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2024. (32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings).

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abstract = "With the emergence of quantum computers, traditional open key cryptographic schemes have faced an existential threat that necessitates the development of quantum resistant algorithms. Post Quantum Cryptography (PQC) has emerged as a solution that opposes this new cryptoanalytic evolution with hash based signature schemes such as SPHINCS+, known as one of the leading candidates by NIST. However, SPHINCS+ requires hardware acceleration for practical use. This study offers a method to accelerate the SPHINCS+ algorithm running in the RISC-V processor on the FPGA using the LLVM integration for custom instruction extension. Custom instructions have been developed for the SHA-256 operations, a fundamental component of SPHINCS+, resulting in a 5.09x acceleration of the algorithm.",

keywords = "LLVM, Post Quantum Cryptography (PQC), RISC-V, SHA-256 optimization, SPHINCS+, custom instructions, hardware acceleration, vector instructions",

author = "{\c C}ukur, \{Mert Pa{\c s}a\} and G{\"u}ne{\c s}, \{Ece Olcay\}",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 ; Conference date: 15-05-2024 Through 18-05-2024",

year = "2024",

doi = "10.1109/SIU61531.2024.10600793",

language = "T{\"u}rk{\c c}e",

series = "32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Çukur, MP & Güneş, EO 2024, RISC-V İşlemcisi Üzerinde Özel Komutlar ve LLVM Entegrasyonu ile SPHINCS+ PQC Algoritmasının Optimizasyonu. in 32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings. 32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024, Mersin, Türkiye, 15/05/24. https://doi.org/10.1109/SIU61531.2024.10600793

RISC-V İşlemcisi Üzerinde Özel Komutlar ve LLVM Entegrasyonu ile SPHINCS+ PQC Algoritmasının Optimizasyonu. / Çukur, Mert Paşa; Güneş, Ece Olcay.
32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2024. (32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings).

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

TY - GEN

T1 - RISC-V İşlemcisi Üzerinde Özel Komutlar ve LLVM Entegrasyonu ile SPHINCS+ PQC Algoritmasının Optimizasyonu

AU - Çukur, Mert Paşa

AU - Güneş, Ece Olcay

PY - 2024

Y1 - 2024

N2 - With the emergence of quantum computers, traditional open key cryptographic schemes have faced an existential threat that necessitates the development of quantum resistant algorithms. Post Quantum Cryptography (PQC) has emerged as a solution that opposes this new cryptoanalytic evolution with hash based signature schemes such as SPHINCS+, known as one of the leading candidates by NIST. However, SPHINCS+ requires hardware acceleration for practical use. This study offers a method to accelerate the SPHINCS+ algorithm running in the RISC-V processor on the FPGA using the LLVM integration for custom instruction extension. Custom instructions have been developed for the SHA-256 operations, a fundamental component of SPHINCS+, resulting in a 5.09x acceleration of the algorithm.

AB - With the emergence of quantum computers, traditional open key cryptographic schemes have faced an existential threat that necessitates the development of quantum resistant algorithms. Post Quantum Cryptography (PQC) has emerged as a solution that opposes this new cryptoanalytic evolution with hash based signature schemes such as SPHINCS+, known as one of the leading candidates by NIST. However, SPHINCS+ requires hardware acceleration for practical use. This study offers a method to accelerate the SPHINCS+ algorithm running in the RISC-V processor on the FPGA using the LLVM integration for custom instruction extension. Custom instructions have been developed for the SHA-256 operations, a fundamental component of SPHINCS+, resulting in a 5.09x acceleration of the algorithm.

KW - LLVM

KW - Post Quantum Cryptography (PQC)

KW - RISC-V

KW - SHA-256 optimization

KW - SPHINCS+

KW - custom instructions

KW - hardware acceleration

KW - vector instructions

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DO - 10.1109/SIU61531.2024.10600793

M3 - Konferans katkısı

AN - SCOPUS:85200846336

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BT - 32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024

Y2 - 15 May 2024 through 18 May 2024

ER -

Çukur MP, Güneş EO. RISC-V İşlemcisi Üzerinde Özel Komutlar ve LLVM Entegrasyonu ile SPHINCS+ PQC Algoritmasının Optimizasyonu. In 32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2024. (32nd IEEE Conference on Signal Processing and Communications Applications, SIU 2024 - Proceedings). doi: 10.1109/SIU61531.2024.10600793

RISC-V İşlemcisi Üzerinde Özel Komutlar ve LLVM Entegrasyonu ile SPHINCS+ PQC Algoritmasının Optimizasyonu

Özet

Yayın serisi

???event.eventtypes.event.conference???

Bibliyografik not

Keywords

Belgeye Erişim

Diğer Dosyalar ve Linkler

Parmak izi

Alıntı Yap