Review: Analog design methodologies for reliability in nanoscale CMOS circuits

Engin Afacan, Mustafa Berke Yelten, Gunhan Dundar

Araştırma sonucu: ???type-name???Konferans katkısıbilirkişi

20 Atıf (Scopus)

Özet

In modern CMOS technology, local electrical stress has substantially increased as device geometries scaled down more aggressively compared to supply voltages. As a result, time-dependent degradation mechanisms (aging phenomena) became an important performance problem, which leads to a considerable lifetime reduction in manufactured integrated circuits. Combination of these aging phenomena with process variations has made reliability a major design objective. In analog circuits, different approaches have been proposed to mitigate the performance challenges related to device reliability. This paper discusses aging in CMOS technology and reviews reliability-aware analog circuit design methodologies for nanoscale circuits.

Orijinal dilİngilizce
Ana bilgisayar yayını başlığıSMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
YayınlayanInstitute of Electrical and Electronics Engineers Inc.
ISBN (Elektronik)9781509050529
DOI'lar
Yayın durumuYayınlandı - 14 Tem 2017
Etkinlik14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017 - Giardini Naxos, Taormina, Italy
Süre: 12 Haz 201715 Haz 2017

Yayın serisi

AdıSMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design

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???event.eventtypes.event.conference???14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017
Ülke/BölgeItaly
ŞehirGiardini Naxos, Taormina
Periyot12/06/1715/06/17

Bibliyografik not

Publisher Copyright:
© 2017 IEEE.

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