Reliability and security of arbiter-based physical unclonable function circuits

Physical unclonable functions (PUFs) are considered as a promising technology that would be used for secure key generation and storage, integrated circuit (IC) authentication, and chip-unique signature generation. On the basis of the delay variation of logic gates across ICs, PUF circuits could be used to generate secret keys attached to some challenge-response schemes. In this study, an arbiter-based PUF circuit is implemented on Xilinx Virtex 2 Pro field-programmable gate array (Xilinx, Inc., San Jose, CA, USA), and its identification capability, reliability, and security are investigated. For this purpose, we define and measure the parameters such as interchip variation and environmental noise, which are important in the identification process of different ICs. In order to test the resistance of PUF circuit against software attacks, we applied two approaches. In the first one, we use a support vector machine classifier, and attacks are considered as a classification problem. In the second one, linear programming technique is applied to find the delay variables corresponding to the linear model of the PUF circuit.