Reconvergent Path-aware Simulation of Bit-stream Processing

Sercan Aygun; M. Hassan Najafi; Mohsen Imani; Ece Olcay Gunes

doi:10.1145/3583781.3590323

Reconvergent Path-aware Simulation of Bit-stream Processing

Sercan Aygun
, M. Hassan Najafi
, Mohsen Imani
, Ece Olcay Gunes

Elektronik ve Hab.Müh.Bölümü

University of Louisiana at Lafayette
University of California at Irvine

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

Özet

Few studies have explored the complex circuit simulation of stochastic and unary computing systems, which are referred to under the umbrella term of bit-stream processing. The computer simulation of multi-level cascaded circuits with reconvergent paths has not been largely examined in the context of bit-stream processing systems. This study addresses this gap and proposes a contingency table -based reconvergent path-aware simulation method for fast and efficient simulation of multi-level circuits. The proposed method exhibits significantly better runtime and accuracy.

Orijinal dil	İngilizce
Ana bilgisayar yayını başlığı	GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023
Yayınlayan	Association for Computing Machinery
Sayfalar	225-226
Sayfa sayısı	2
ISBN (Elektronik)	9798400701252
DOI'lar	https://doi.org/10.1145/3583781.3590323
Yayın durumu	Yayınlandı - 5 Haz 2023
Etkinlik	33rd Great Lakes Symposium on VLSI, GLSVLSI 2023 - Knoxville, United States Süre: 5 Haz 2023 → 7 Haz 2023

Yayın serisi

Adı	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	33rd Great Lakes Symposium on VLSI, GLSVLSI 2023
Ülke/Bölge	United States
Şehir	Knoxville
Periyot	5/06/23 → 7/06/23

Bibliyografik not

Publisher Copyright:
© 2023 Owner/Author.

Finansman

This work was supported in part by National Science Foundation (NSF) grants #2127780 and #2019511, Semiconductor Research Corporation (SRC), O ce of Naval Research, grant #N00014-21-1-2225 and #N00014-22-1-2067, the Air Force O ce of Scientific Research under award #FA9550-22-1-0253, the Louisiana Board of Regents Support Fund #LEQSF(2020-23)-RD-A-26, and generous gifts from Cisco, Xilinx, and Nvidia. This work was supported in part by National Science Foundation (NSF) grants #2127780 and #2019511, Semiconductor Research Corporation (SRC), Office of Naval Research, grant #N00014-21-1-2225 and #N00014-22-1-2067, the Air Force Office of Scientific Research under award #FA9550-22-1-0253, the Louisiana Board of Regents Support Fund #LEQSF(2020-23)-RD-A-26, and generous gifts from Cisco, Xilinx, and Nvidia.

Finansörler	Finansör numarası
Air Force O ce of Scientific Research
O ce of Naval Research
National Science Foundation	2019511, 2127780
Office of Naval Research	00014-21-1-2225, 00014-22-1-2067
Semiconductor Research Corporation
Air Force Office of Scientific Research	9550-22-1-0253
Louisiana Board of Regents	2020-23)-RD-A-26

Belgeye Erişim

10.1145/3583781.3590323

Diğer Dosyalar ve Linkler

Link to publication in Scopus

Alıntı Yap

@inproceedings{29a8271b8b2843e8a8b1460ef7f73403,

title = "Reconvergent Path-aware Simulation of Bit-stream Processing",

abstract = "Few studies have explored the complex circuit simulation of stochastic and unary computing systems, which are referred to under the umbrella term of bit-stream processing. The computer simulation of multi-level cascaded circuits with reconvergent paths has not been largely examined in the context of bit-stream processing systems. This study addresses this gap and proposes a contingency table -based reconvergent path-aware simulation method for fast and efficient simulation of multi-level circuits. The proposed method exhibits significantly better runtime and accuracy.",

keywords = "bit-stream processing, reconvergence, simulation",

author = "Sercan Aygun and Najafi, \{M. Hassan\} and Mohsen Imani and Gunes, \{Ece Olcay\}",

note = "Publisher Copyright: {\textcopyright} 2023 Owner/Author.; 33rd Great Lakes Symposium on VLSI, GLSVLSI 2023 ; Conference date: 05-06-2023 Through 07-06-2023",

year = "2023",

month = jun,

day = "5",

doi = "10.1145/3583781.3590323",

language = "English",

series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

publisher = "Association for Computing Machinery",

pages = "225--226",

booktitle = "GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023",

}

Aygun, S, Najafi, MH, Imani, M & Gunes, EO 2023, Reconvergent Path-aware Simulation of Bit-stream Processing. in GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, Association for Computing Machinery, pp. 225-226, 33rd Great Lakes Symposium on VLSI, GLSVLSI 2023, Knoxville, United States, 5/06/23. https://doi.org/10.1145/3583781.3590323

Reconvergent Path-aware Simulation of Bit-stream Processing. / Aygun, Sercan; Najafi, M. Hassan; Imani, Mohsen et al.
GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023. Association for Computing Machinery, 2023. p. 225-226 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

TY - GEN

T1 - Reconvergent Path-aware Simulation of Bit-stream Processing

AU - Aygun, Sercan

AU - Najafi, M. Hassan

AU - Imani, Mohsen

AU - Gunes, Ece Olcay

PY - 2023/6/5

Y1 - 2023/6/5

N2 - Few studies have explored the complex circuit simulation of stochastic and unary computing systems, which are referred to under the umbrella term of bit-stream processing. The computer simulation of multi-level cascaded circuits with reconvergent paths has not been largely examined in the context of bit-stream processing systems. This study addresses this gap and proposes a contingency table -based reconvergent path-aware simulation method for fast and efficient simulation of multi-level circuits. The proposed method exhibits significantly better runtime and accuracy.

AB - Few studies have explored the complex circuit simulation of stochastic and unary computing systems, which are referred to under the umbrella term of bit-stream processing. The computer simulation of multi-level cascaded circuits with reconvergent paths has not been largely examined in the context of bit-stream processing systems. This study addresses this gap and proposes a contingency table -based reconvergent path-aware simulation method for fast and efficient simulation of multi-level circuits. The proposed method exhibits significantly better runtime and accuracy.

KW - bit-stream processing

KW - reconvergence

KW - simulation

UR - https://www.scopus.com/pages/publications/85163207128

U2 - 10.1145/3583781.3590323

DO - 10.1145/3583781.3590323

M3 - Conference contribution

AN - SCOPUS:85163207128

T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

SP - 225

EP - 226

BT - GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023

PB - Association for Computing Machinery

T2 - 33rd Great Lakes Symposium on VLSI, GLSVLSI 2023

Y2 - 5 June 2023 through 7 June 2023

ER -

Reconvergent Path-aware Simulation of Bit-stream Processing

Özet

Yayın serisi

???event.eventtypes.event.conference???

Bibliyografik not

Finansman

Belgeye Erişim

Diğer Dosyalar ve Linkler

Parmak izi

Alıntı Yap