Power analysis resistant hardware implementations of AES

Levent Ordu*, Berna Örs

*Bu çalışma için yazışmadan sorumlu yazar

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3 Atıf (Scopus)

Özet

This paper presents the first FPGA implementation of the Advanced Encryption Standard (AES) with masking countermeasure for the power analysis (PA) attacks. PA is a powerful side-channel analysis (SCA) attack. A side-channel analysis (SCA) attack takes advantage of implementation specific characteristics to recover the secret parameters involved in the computation. The goals of side-channel attack countermeasures are reducing the correlation between the side-channel data and the secret data. Data masking is one of the most powerful countermeasure against side channel attacks. The message and the key are masked with some random values at the beginning of computations. We have implemented the AES algorithm on an FPGA by using two different masking method: multiplicative and additive.

Orijinal dilİngilizce
Ana bilgisayar yayını başlığıICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
Sayfalar1408-1411
Sayfa sayısı4
DOI'lar
Yayın durumuYayınlandı - 2007
Etkinlik14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco
Süre: 11 Ara 200714 Ara 2007

Yayın serisi

AdıProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

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???event.eventtypes.event.conference???14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
Ülke/BölgeMorocco
ŞehirMarrakech
Periyot11/12/0714/12/07

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