Özet
In this paper, we investigate the design and implementation aspects of 1-level DWT by employing a finite impulse response (FIR) filter on FPGA platform. We estimate the performance requirements and hardware resources for two key multiplication-free architectures, namely, distributed arithmetic algorithm (DAA) and residue number system (RNS), allowing for selection of the proper algorithm and implementation of DAA and RNS-based DWT. The design has been implemented and synthesized in Xilinx ZYNQ-7000 FPGA, taking advantage of embedded block RAMs (BRAMs). The results show that the DAA-based approach is appropriate and feasible for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps.
Orijinal dil | İngilizce |
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Ana bilgisayar yayını başlığı | 2017 10th International Conference on Electrical and Electronics Engineering, ELECO 2017 |
Yayınlayan | Institute of Electrical and Electronics Engineers Inc. |
Sayfalar | 1122-1126 |
Sayfa sayısı | 5 |
ISBN (Elektronik) | 9786050107371 |
Yayın durumu | Yayınlandı - 2 Tem 2017 |
Etkinlik | 10th International Conference on Electrical and Electronics Engineering, ELECO 2017 - Bursa, Turkey Süre: 29 Kas 2017 → 2 Ara 2017 |
Yayın serisi
Adı | 2017 10th International Conference on Electrical and Electronics Engineering, ELECO 2017 |
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Hacim | 2018-January |
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???event.eventtypes.event.conference??? | 10th International Conference on Electrical and Electronics Engineering, ELECO 2017 |
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Ülke/Bölge | Turkey |
Şehir | Bursa |
Periyot | 29/11/17 → 2/12/17 |
Bibliyografik not
Publisher Copyright:© 2017 EMO (Turkish Chamber of Electrical Enginners).