Multiplier-less 1-level discrete wavelet transform implementations on ZC706 development kit

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3 Atıf (Scopus)

Özet

In this paper, we investigate the design and implementation aspects of 1-level DWT by employing a finite impulse response (FIR) filter on FPGA platform. We estimate the performance requirements and hardware resources for two key multiplication-free architectures, namely, distributed arithmetic algorithm (DAA) and residue number system (RNS), allowing for selection of the proper algorithm and implementation of DAA and RNS-based DWT. The design has been implemented and synthesized in Xilinx ZYNQ-7000 FPGA, taking advantage of embedded block RAMs (BRAMs). The results show that the DAA-based approach is appropriate and feasible for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps.

Orijinal dilİngilizce
Ana bilgisayar yayını başlığı2017 10th International Conference on Electrical and Electronics Engineering, ELECO 2017
YayınlayanInstitute of Electrical and Electronics Engineers Inc.
Sayfalar1122-1126
Sayfa sayısı5
ISBN (Elektronik)9786050107371
Yayın durumuYayınlandı - 2 Tem 2017
Etkinlik10th International Conference on Electrical and Electronics Engineering, ELECO 2017 - Bursa, Turkey
Süre: 29 Kas 20172 Ara 2017

Yayın serisi

Adı2017 10th International Conference on Electrical and Electronics Engineering, ELECO 2017
Hacim2018-January

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???event.eventtypes.event.conference???10th International Conference on Electrical and Electronics Engineering, ELECO 2017
Ülke/BölgeTurkey
ŞehirBursa
Periyot29/11/172/12/17

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Publisher Copyright:
© 2017 EMO (Turkish Chamber of Electrical Enginners).

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