MOS-only Meminductor with Experimental Verification

This work introduces a simple meminductor emulator realized exclusively with MOS-based components. The proposed architecture exploits the inherent capacitances of MOSFET devices instead of bulky passive elements, thereby reducing their impact on integrated circuit implementations. The validity of the theoretical analysis is confirmed through comprehensive simulations performed in the Cadence environment using the 0.18 μm CMOS process. In addition to demonstrating its use within a chaotic oscillator, the proposed meminductor emulator is also integrated into an adaptive learning circuit to highlight its capability in learning-oriented and bio-inspired applications. Finally, experimental investigations are carried out to further substantiate the practical feasibility of the circuit.