TY - GEN
T1 - Linearly weighted classifier circuit
AU - Yildiz, Merih
AU - Minaei, Shahram
AU - Özoǧuz, Serdar
PY - 2009
Y1 - 2009
N2 - In this paper a CMOS realization of a linearly weighted classifier circuit which is called classifier block is proposed. The proposed classifier block is composed of Linearly Weighted Circuits (LWC) and CMOS Core Circuits (CC). The proposed circuit can classify linearly non-separable data. The weights of the classifier circuit are achieved with LWC blocks. Using 0.35 um AMS technology parameters, SPICE simulation results for a LWC and classifier block are included to verify the expected results.
AB - In this paper a CMOS realization of a linearly weighted classifier circuit which is called classifier block is proposed. The proposed classifier block is composed of Linearly Weighted Circuits (LWC) and CMOS Core Circuits (CC). The proposed circuit can classify linearly non-separable data. The weights of the classifier circuit are achieved with LWC blocks. Using 0.35 um AMS technology parameters, SPICE simulation results for a LWC and classifier block are included to verify the expected results.
KW - Classifier, linearly non-separable, cmos
UR - http://www.scopus.com/inward/record.url?scp=72249096892&partnerID=8YFLogxK
U2 - 10.1109/NEWCAS.2009.5290438
DO - 10.1109/NEWCAS.2009.5290438
M3 - Conference contribution
AN - SCOPUS:72249096892
SN - 9781424445738
T3 - 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
BT - 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
T2 - 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
Y2 - 28 June 2009 through 1 July 2009
ER -