Instruction Extension of RV32I and GCC Back End for Ascon Lightweight Cryptography Algorithm

Lightweight cryptography is useful to provide security and privacy in resource constraint embedded devices. Latency and memory consumption are the key elements in performance metrics for lightweight cryptography algorithm implementations. Ascon lightweight cryptography algorithm is one of the finalists in CEASAR competition. In this study, special cryptographic non-standard RISC-V instructions have been developed in order to reduce the required number of clock cycles and instruction memory for the execution of the algorithm on RV32I based processors. A profiling methodology has been developed to choose the best special instruction for achieving the highest benefit in performance. An end-To-end test environment has been formed by extending the GNU Compiler Collection and Spike RISC-V ISA Simulator for the special cryptographic instruction extensions of RISC-V processors. New intrinsic functions and instruction patterns for the new instructions have been integrated into the GCC RISC-V back end. Spike has been modified with the new instructions to run the program. The algorithm has been analysed with the proposed instructions and different optimization flags and improvement results have been shown in this study.