Implementation of a chaotic time-delay RNG based secure communication system on FPGA

Security is one of the most important design parameters in communication systems. Security of cryptographic systems depends on the unpredictability of keys. Chaotic random number generators have become an alternative method for random number generation instead of physical noise based ones. In this work, we describe a system-on-chip design which includes a chaos-based random number generator. Key generation, encryption-decryption blocks and control unit are designed to run on the same chip. All blocks are connected to the Microblaze softcore processor and implemented on a Xilinx FPGA. Structural details of the system and the results are shared.