Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi

Hakan Aktaş; Refik Sever; Behçet Uʇur Töreyin

doi:10.1109/SIU.2015.7130315

Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi

Hakan Aktaş
, Refik Sever
, Behçet Uʇur Töreyin

Akdeniz University
Cankaya University

Araştırma çıktısı: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › Hakem

2 Atıf (Scopus)

Özet

In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs.

Tercüme edilen katkı başlığı	A two stage template matching algorithm and its Implementation on FPGA
Orijinal dil	Türkçe
Ana bilgisayar yayını başlığı	2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings
Yayınlayan	Institute of Electrical and Electronics Engineers Inc.
Sayfalar	2214-2217
Sayfa sayısı	4
ISBN (Elektronik)	9781467373869
DOI'lar	https://doi.org/10.1109/SIU.2015.7130315
Yayın durumu	Yayınlandı - 19 Haz 2015
Harici olarak yayınlandı	Evet
Etkinlik	2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Malatya, Türkiye Süre: 16 May 2015 → 19 May 2015

Yayın serisi

Adı	2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	2015 23rd Signal Processing and Communications Applications Conference, SIU 2015
Ülke/Bölge	Türkiye
Şehir	Malatya
Periyot	16/05/15 → 19/05/15

Bibliyografik not

Publisher Copyright:
© 2015 IEEE.

Keywords

Field-Programmable-Gate-Array (FPGA)
Memorry Adressing
Parallel Processing
Sum of Absolute Differences
Template Matching
Unmanned Air Vehicle (UAV)

Belgeye Erişim

10.1109/SIU.2015.7130315

Diğer Dosyalar ve Linkler

Link to publication in Scopus

Alıntı Yap

Aktaş, H., Sever, R., & Töreyin, B. U. (2015). Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi. In 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings (pp. 2214-2217). Makale 7130315 (2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SIU.2015.7130315

Aktaş, Hakan ; Sever, Refik ; Töreyin, Behçet Uʇur. / Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi. 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 2214-2217 (2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings).

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title = "Iki A{\c s}amali {\c S}ablon E{\c s}le{\c s}tirme Algoritmasi ve Y{\"u}ksek Hizli FPGA Ger{\c c}eklemesi",

abstract = "In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs.",

keywords = "Field-Programmable-Gate-Array (FPGA), Memorry Adressing, Parallel Processing, Sum of Absolute Differences, Template Matching, Unmanned Air Vehicle (UAV)",

author = "Hakan Akta{\c s} and Refik Sever and T{\"o}reyin, \{Beh{\c c}et Uʇur\}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 ; Conference date: 16-05-2015 Through 19-05-2015",

year = "2015",

month = jun,

day = "19",

doi = "10.1109/SIU.2015.7130315",

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series = "2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings",

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Aktaş, H, Sever, R & Töreyin, BU 2015, Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi. in 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings., 7130315, 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 2214-2217, 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015, Malatya, Türkiye, 16/05/15. https://doi.org/10.1109/SIU.2015.7130315

Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi. / Aktaş, Hakan; Sever, Refik; Töreyin, Behçet Uʇur.
2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. p. 2214-2217 7130315 (2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings).

Araştırma çıktısı: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › Hakem

TY - GEN

T1 - Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi

AU - Aktaş, Hakan

AU - Sever, Refik

AU - Töreyin, Behçet Uʇur

PY - 2015/6/19

Y1 - 2015/6/19

N2 - In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs.

AB - In this paper, to decrease the computational cost and number of cycles in Template Matching Algorithm, a novel two-stage algorithm is proposed. The Sum of Absolute Differences method is used for matching. The proposed algorithm is implemented on Field-Programmable-Gate-Array (FPGA). The algorithm is accelerated with the effective usage of Block RAMs distributed on FPGA. Thus, the proposed algorithm became fast enough for real time object tracking applications on UAVs.

KW - Field-Programmable-Gate-Array (FPGA)

KW - Memorry Adressing

KW - Parallel Processing

KW - Sum of Absolute Differences

KW - Template Matching

KW - Unmanned Air Vehicle (UAV)

UR - https://www.scopus.com/pages/publications/84939170749

U2 - 10.1109/SIU.2015.7130315

DO - 10.1109/SIU.2015.7130315

M3 - Konferans katkısı

AN - SCOPUS:84939170749

T3 - 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings

SP - 2214

EP - 2217

BT - 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015

Y2 - 16 May 2015 through 19 May 2015

ER -

Aktaş H, Sever R, Töreyin BU. Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi. In 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2015. p. 2214-2217. 7130315. (2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings). doi: 10.1109/SIU.2015.7130315

Iki Aşamali Şablon Eşleştirme Algoritmasi ve Yüksek Hizli FPGA Gerçeklemesi

Özet

Yayın serisi

???event.eventtypes.event.conference???

Bibliyografik not

Keywords

Belgeye Erişim

Diğer Dosyalar ve Linkler

Parmak izi

Alıntı Yap