HW/SW Design Space Exploration of A Complementary Filter on Zynq SoC

In this paper, a Complementary Filter (CF) for pitch and roll angle estimation based on linear acceleration and angular rate measurements is designed and implemented on a Xilinx Zynq System-on-Chip (SoC) device. The CF is modelled in Simulink. Its C code and HDL code is generated by the Embedded Coder and the HDL coder, respectively. Filter input and output interface is constituted by a Hardware Abstraction Layer (HAL) which is manually designed and implemented on the Processing Logic (PL) of the SoC. The performance analysis of hardware/software (HW/SW) implementations of the CF is presented aiming realtime operation. The results of dual-core ARM Cortex-A9 Processing System (PS) running the stock PetaLinux kernel is presented with different task priority conditions, CPU loads, and sleep policies. The real-time performance of Linux based designs are compared with the baremetal SW implementation and absolute HW implementation. The timing is conducted on both SW and HW sides in the designs utilizing the PS. Hence, the data transfer overhead between HW and SW is also revealed. A simple adaptive task sleep approach utilizing PL based counter is proposed for CPU utilization efficiency.