Hardware implementation of a Montgomery modular multiplier in a systolic array

Siddika Berna Örs; Lejla Batina; Bart Preneel; Joos Vandewalle

doi:10.1109/IPDPS.2003.1213341

Hardware implementation of a Montgomery modular multiplier in a systolic array

Siddika Berna Örs
, Lejla Batina
, Bart Preneel
, Joos Vandewalle

KU Leuven
SafeNet BV

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

46 Atıf (Scopus)

Özet

This paper describes a hardware architecture for modular multiplication operation which is efficient for bit-lengths suitable for both commonly used types of public key cryptography (PKC) i.e. ECC and RSA cryptosystems. The challenge of current PKC implementations is to deal with long numbers (160-2048 bits) in order to achieve system's efficiency, as well as security. RSA, still the most popular PKC, has at its root the modular exponentiation operation. Modular exponentiation consists of repeated modular multiplications, which is also the basic operation for ECC protocols. The solution proposed in this work uses a systolic array implementation and can be used for arbitrary precisions. We also present modular exponentiation based on Montgomery's Multiplication Method (MMM).

Orijinal dil	İngilizce
Ana bilgisayar yayını başlığı	Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003
Yayınlayan	Institute of Electrical and Electronics Engineers Inc.
ISBN (Elektronik)	0769519261, 9780769519265
DOI'lar	https://doi.org/10.1109/IPDPS.2003.1213341
Yayın durumu	Yayınlandı - 2003
Harici olarak yayınlandı	Evet
Etkinlik	International Parallel and Distributed Processing Symposium, IPDPS 2003 - Nice, France Süre: 22 Nis 2003 → 26 Nis 2003

Yayın serisi

Adı	Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	International Parallel and Distributed Processing Symposium, IPDPS 2003
Ülke/Bölge	France
Şehir	Nice
Periyot	22/04/03 → 26/04/03

Bibliyografik not

Publisher Copyright:
© 2003 IEEE.

Belgeye Erişim

10.1109/IPDPS.2003.1213341

Diğer Dosyalar ve Linkler

Link to publication in Scopus

Alıntı Yap

Örs, S. B., Batina, L., Preneel, B., & Vandewalle, J. (2003). Hardware implementation of a Montgomery modular multiplier in a systolic array. In Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003 Makale 1213341 (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPDPS.2003.1213341

Örs, Siddika Berna ; Batina, Lejla ; Preneel, Bart et al. / Hardware implementation of a Montgomery modular multiplier in a systolic array. Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003. Institute of Electrical and Electronics Engineers Inc., 2003. (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003).

@inproceedings{5d62754b2c7e4c799ce2f3e293fc67db,

title = "Hardware implementation of a Montgomery modular multiplier in a systolic array",

abstract = "This paper describes a hardware architecture for modular multiplication operation which is efficient for bit-lengths suitable for both commonly used types of public key cryptography (PKC) i.e. ECC and RSA cryptosystems. The challenge of current PKC implementations is to deal with long numbers (160-2048 bits) in order to achieve system's efficiency, as well as security. RSA, still the most popular PKC, has at its root the modular exponentiation operation. Modular exponentiation consists of repeated modular multiplications, which is also the basic operation for ECC protocols. The solution proposed in this work uses a systolic array implementation and can be used for arbitrary precisions. We also present modular exponentiation based on Montgomery's Multiplication Method (MMM).",

keywords = "ECC, FPGA, Montgomery's Multiplication Method, Public Key Cryptography, RSA, Systolic array",

author = "{\"O}rs, \{Siddika Berna\} and Lejla Batina and Bart Preneel and Joos Vandewalle",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; International Parallel and Distributed Processing Symposium, IPDPS 2003 ; Conference date: 22-04-2003 Through 26-04-2003",

year = "2003",

doi = "10.1109/IPDPS.2003.1213341",

language = "English",

series = "Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003",

address = "United States",

}

Örs, SB, Batina, L, Preneel, B & Vandewalle, J 2003, Hardware implementation of a Montgomery modular multiplier in a systolic array. in Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003., 1213341, Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003, Institute of Electrical and Electronics Engineers Inc., International Parallel and Distributed Processing Symposium, IPDPS 2003, Nice, France, 22/04/03. https://doi.org/10.1109/IPDPS.2003.1213341

Hardware implementation of a Montgomery modular multiplier in a systolic array. / Örs, Siddika Berna; Batina, Lejla; Preneel, Bart et al.
Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003. Institute of Electrical and Electronics Engineers Inc., 2003. 1213341 (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003).

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

TY - GEN

T1 - Hardware implementation of a Montgomery modular multiplier in a systolic array

AU - Örs, Siddika Berna

AU - Batina, Lejla

AU - Preneel, Bart

AU - Vandewalle, Joos

PY - 2003

Y1 - 2003

N2 - This paper describes a hardware architecture for modular multiplication operation which is efficient for bit-lengths suitable for both commonly used types of public key cryptography (PKC) i.e. ECC and RSA cryptosystems. The challenge of current PKC implementations is to deal with long numbers (160-2048 bits) in order to achieve system's efficiency, as well as security. RSA, still the most popular PKC, has at its root the modular exponentiation operation. Modular exponentiation consists of repeated modular multiplications, which is also the basic operation for ECC protocols. The solution proposed in this work uses a systolic array implementation and can be used for arbitrary precisions. We also present modular exponentiation based on Montgomery's Multiplication Method (MMM).

AB - This paper describes a hardware architecture for modular multiplication operation which is efficient for bit-lengths suitable for both commonly used types of public key cryptography (PKC) i.e. ECC and RSA cryptosystems. The challenge of current PKC implementations is to deal with long numbers (160-2048 bits) in order to achieve system's efficiency, as well as security. RSA, still the most popular PKC, has at its root the modular exponentiation operation. Modular exponentiation consists of repeated modular multiplications, which is also the basic operation for ECC protocols. The solution proposed in this work uses a systolic array implementation and can be used for arbitrary precisions. We also present modular exponentiation based on Montgomery's Multiplication Method (MMM).

KW - ECC

KW - FPGA

KW - Montgomery's Multiplication Method

KW - Public Key Cryptography

KW - RSA

KW - Systolic array

UR - https://www.scopus.com/pages/publications/84947236925

U2 - 10.1109/IPDPS.2003.1213341

DO - 10.1109/IPDPS.2003.1213341

M3 - Conference contribution

AN - SCOPUS:84947236925

T3 - Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

BT - Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - International Parallel and Distributed Processing Symposium, IPDPS 2003

Y2 - 22 April 2003 through 26 April 2003

ER -

Örs SB, Batina L, Preneel B, Vandewalle J. Hardware implementation of a Montgomery modular multiplier in a systolic array. In Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003. Institute of Electrical and Electronics Engineers Inc. 2003. 1213341. (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003). doi: 10.1109/IPDPS.2003.1213341

Hardware implementation of a Montgomery modular multiplier in a systolic array

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