Fault tolerant register file design for MIPS AES-crypto microprocessor

This paper represents a new method to protect register file of a RISC microprocessor against MBUs. The key idea is combining the most important properties of two methods in the literature. One of them is a type of information redundancy called as matrix code that has detection and correction capability. The other one is TMR which is a widely used hardware redundancy technique and masks faults. The microprocessor has been designed as a 32-bit single cycle MIPS architecture. Moreover, a crypto module has been designed and integrated into the microprocessor and AES-128 algorithm is implemented in order to create an application platform. The proposed method can detect and correct up to 2, 4, 8-burst or random errors in any register based on the dataset configuration. This design has been implemented in Xilinx Virtex-5 FPGA. Area and power consumption has been compared. The method is applicable for register files with different sizes.