Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks

Mohammadreza Esmali Nojehdeh; Sajjad Parvin; Mustafa Altun

doi:10.1109/ISVLSI51109.2021.00079

Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks

Mohammadreza Esmali Nojehdeh
, Sajjad Parvin
, Mustafa Altun

Elektronik ve Hab.Müh.Bölümü

Istanbul Technical University

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

4 Atıf (Scopus)

Özet

In this paper, we propose an efficient method to realize a convolution layer of the convolution neural networks (CNNs). Inspired by the fully-connected neural network architecture, we introduce an efficient computation approach to implement convolution operations. Also, to reduce hardware complexity, we implement convolutional layers under the time-multiplexed architecture where computing resources are re-used in the multiply-accumulate (MAC) blocks. A comprehensive evaluation of convolution layers shows using our proposed method when compared to the conventional MAC-based method results up to 97% and 50% reduction in dissipated power and computation time, respectively.

Orijinal dil	İngilizce
Ana bilgisayar yayını başlığı	Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021
Yayınlayan	IEEE Computer Society
Sayfalar	402-405
Sayfa sayısı	4
ISBN (Elektronik)	9781665439466
DOI'lar	https://doi.org/10.1109/ISVLSI51109.2021.00079
Yayın durumu	Yayınlandı - Tem 2021
Etkinlik	20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021 - Tampa, United States Süre: 7 Tem 2021 → 9 Tem 2021

Yayın serisi

Adı	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Hacim	2021-July
ISSN (Basılı)	2159-3469
ISSN (Elektronik)	2159-3477

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021
Ülke/Bölge	United States
Şehir	Tampa
Periyot	7/07/21 → 9/07/21

Bibliyografik not

Publisher Copyright:
© 2021 IEEE.

Finansman

ACKNOWLDGEMENT This work is supported by the TUBITAK-1001 projects #119E507 and Istanbul Technical University BAP projects #42446.

Finansörler	Finansör numarası
TUBITAK-1001	119E507
Istanbul Teknik Üniversitesi	42446

Belgeye Erişim

10.1109/ISVLSI51109.2021.00079

Diğer Dosyalar ve Linkler

Link to publication in Scopus

Alıntı Yap

Nojehdeh, M. E., Parvin, S., & Altun, M. (2021). Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks. In Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021 (pp. 402-405). (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Hac. 2021-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI51109.2021.00079

@inproceedings{e2893fb4b4334f0092fd768eb21e4f26,

title = "Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks",

abstract = "In this paper, we propose an efficient method to realize a convolution layer of the convolution neural networks (CNNs). Inspired by the fully-connected neural network architecture, we introduce an efficient computation approach to implement convolution operations. Also, to reduce hardware complexity, we implement convolutional layers under the time-multiplexed architecture where computing resources are re-used in the multiply-accumulate (MAC) blocks. A comprehensive evaluation of convolution layers shows using our proposed method when compared to the conventional MAC-based method results up to 97\% and 50\% reduction in dissipated power and computation time, respectively.",

author = "Nojehdeh, \{Mohammadreza Esmali\} and Sajjad Parvin and Mustafa Altun",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021 ; Conference date: 07-07-2021 Through 09-07-2021",

year = "2021",

month = jul,

doi = "10.1109/ISVLSI51109.2021.00079",

language = "English",

series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",

publisher = "IEEE Computer Society",

pages = "402--405",

booktitle = "Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021",

address = "United States",

}

Nojehdeh, ME, Parvin, S & Altun, M 2021, Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks. in Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021. Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, hac. 2021-July, IEEE Computer Society, pp. 402-405, 20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021, Tampa, United States, 7/07/21. https://doi.org/10.1109/ISVLSI51109.2021.00079

Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks. / Nojehdeh, Mohammadreza Esmali; Parvin, Sajjad; Altun, Mustafa.
Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021. IEEE Computer Society, 2021. p. 402-405 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Hac. 2021-July).

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

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PY - 2021/7

Y1 - 2021/7

N2 - In this paper, we propose an efficient method to realize a convolution layer of the convolution neural networks (CNNs). Inspired by the fully-connected neural network architecture, we introduce an efficient computation approach to implement convolution operations. Also, to reduce hardware complexity, we implement convolutional layers under the time-multiplexed architecture where computing resources are re-used in the multiply-accumulate (MAC) blocks. A comprehensive evaluation of convolution layers shows using our proposed method when compared to the conventional MAC-based method results up to 97% and 50% reduction in dissipated power and computation time, respectively.

AB - In this paper, we propose an efficient method to realize a convolution layer of the convolution neural networks (CNNs). Inspired by the fully-connected neural network architecture, we introduce an efficient computation approach to implement convolution operations. Also, to reduce hardware complexity, we implement convolutional layers under the time-multiplexed architecture where computing resources are re-used in the multiply-accumulate (MAC) blocks. A comprehensive evaluation of convolution layers shows using our proposed method when compared to the conventional MAC-based method results up to 97% and 50% reduction in dissipated power and computation time, respectively.

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U2 - 10.1109/ISVLSI51109.2021.00079

DO - 10.1109/ISVLSI51109.2021.00079

M3 - Conference contribution

AN - SCOPUS:85114961607

T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

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EP - 405

BT - Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021

PB - IEEE Computer Society

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ER -

Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks

Özet

Yayın serisi

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Bibliyografik not

Finansman

Belgeye Erişim

Diğer Dosyalar ve Linkler

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