Design of the Digital Control Block of an Analog Beamformer Suitable for Ultrasound Applications

An analog beamformer for ultrasound receivers is designed at the system level, aiming for a high signal-to-noise ratio (SNR), a small chip area, and low power dissipation. The transducer structure used as the receiver has eight channels. The SUB-BF method was used in the analog beamformer structure to obtain a high SNR value. The control logic block, the most challenging part of the design, produces clocks with a fine delay resolution of 6.25 ns. The control logic block consists of a delay-locked loop, a duty cycle adjustment circuit, and a phase selector circuit. Clocks with 16 different delays generated by the delay-locked loop are sent to the phase selector circuit, and the selection process is performed according to the bit sequences sent by an external FPGA. All delay information was obtained using mathematical models with the support of the Matlab environment. 6.25 ns resolution and a maximum delay of 680 ns were acquired for this ABF using the parameters as the beam-steering angle of ± 30°, the carrier frequency of 2.5 MHz with a wavelength (λ_c) of 600 μm, target area between 1 cm - 6 cm, and the distance between focal points of λ_c/8.