Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT)

Sadik Iik; Fikret Basar Gencer; Mustafa Berke Yelten

doi:10.1109/SMACD.2018.8434894

Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT)

Sadik Iik, Fikret Basar Gencer, Mustafa Berke Yelten

Elektronik ve Hab.Müh.Bölümü

Istanbul Technical University

Araştırma sonucu: ???type-name??? › Konferans katkısı › bilirkişi

Özet

In this paper, a p-type channel TFT device with 6 terminals (4 gates, one drain and one source) has been proposed. The device has been constructed through Sentaurus TCAD suite. Simple logic gates (NOR, NAND, NOT and XOR) are built by using different input configurations applied to four gates of the device. Device simulations have revealed that all gates can operate at 5 V with full functionality. The performance of the logic gates has been shown to be good enough for simple applications in the large-area digital electronics systems.

Orijinal dil	İngilizce
Ana bilgisayar yayını başlığı	SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
Yayınlayan	Institute of Electrical and Electronics Engineers Inc.
Sayfalar	77-80
Sayfa sayısı	4
ISBN (Basılı)	9781538651520
DOI'lar	https://doi.org/10.1109/SMACD.2018.8434894
Yayın durumu	Yayınlandı - 13 Ağu 2018
Etkinlik	15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018 - Prague, Czech Republic Süre: 2 Tem 2018 → 5 Tem 2018

Yayın serisi

Adı	SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018
Ülke/Bölge	Czech Republic
Şehir	Prague
Periyot	2/07/18 → 5/07/18

Bibliyografik not

Publisher Copyright:
© 2018 IEEE.

Belgeye Erişim

10.1109/SMACD.2018.8434894

Diğer Dosyalar ve Linkler

Link to publication in Scopus

Alıntı Yap

Iik, S., Gencer, F. B., & Yelten, M. B. (2018). Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT). In SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (pp. 77-80). Makale 8434894 (SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SMACD.2018.8434894

Iik, Sadik ; Gencer, Fikret Basar ; Yelten, Mustafa Berke. / Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT). SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 77-80 (SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design).

@inproceedings{e34e0538686c43f5918b5c7e1903f94c,

title = "Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT)",

abstract = "In this paper, a p-type channel TFT device with 6 terminals (4 gates, one drain and one source) has been proposed. The device has been constructed through Sentaurus TCAD suite. Simple logic gates (NOR, NAND, NOT and XOR) are built by using different input configurations applied to four gates of the device. Device simulations have revealed that all gates can operate at 5 V with full functionality. The performance of the logic gates has been shown to be good enough for simple applications in the large-area digital electronics systems.",

keywords = "large-area electronics, logic gate, multiple gate transistors, TFT",

author = "Sadik Iik and Gencer, {Fikret Basar} and Yelten, {Mustafa Berke}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018 ; Conference date: 02-07-2018 Through 05-07-2018",

year = "2018",

month = aug,

day = "13",

doi = "10.1109/SMACD.2018.8434894",

language = "English",

isbn = "9781538651520",

series = "SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "77--80",

booktitle = "SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design",

address = "United States",

}

Iik, S, Gencer, FB & Yelten, MB 2018, Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT). in SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design., 8434894, SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Institute of Electrical and Electronics Engineers Inc., pp. 77-80, 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018, Prague, Czech Republic, 2/07/18. https://doi.org/10.1109/SMACD.2018.8434894

Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT). / Iik, Sadik; Gencer, Fikret Basar; Yelten, Mustafa Berke.
SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Institute of Electrical and Electronics Engineers Inc., 2018. p. 77-80 8434894 (SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design).

Araştırma sonucu: ???type-name??? › Konferans katkısı › bilirkişi

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T1 - Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT)

AU - Iik, Sadik

AU - Gencer, Fikret Basar

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Y1 - 2018/8/13

N2 - In this paper, a p-type channel TFT device with 6 terminals (4 gates, one drain and one source) has been proposed. The device has been constructed through Sentaurus TCAD suite. Simple logic gates (NOR, NAND, NOT and XOR) are built by using different input configurations applied to four gates of the device. Device simulations have revealed that all gates can operate at 5 V with full functionality. The performance of the logic gates has been shown to be good enough for simple applications in the large-area digital electronics systems.

AB - In this paper, a p-type channel TFT device with 6 terminals (4 gates, one drain and one source) has been proposed. The device has been constructed through Sentaurus TCAD suite. Simple logic gates (NOR, NAND, NOT and XOR) are built by using different input configurations applied to four gates of the device. Device simulations have revealed that all gates can operate at 5 V with full functionality. The performance of the logic gates has been shown to be good enough for simple applications in the large-area digital electronics systems.

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U2 - 10.1109/SMACD.2018.8434894

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Iik S, Gencer FB, Yelten MB. Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT). In SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Institute of Electrical and Electronics Engineers Inc. 2018. p. 77-80. 8434894. (SMACD 2018 - 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design). doi: 10.1109/SMACD.2018.8434894

Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT)

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