Design and Verification of A Single-Cycle RISC-V Core Using MATLAB Simulink

Model-based hardware design approaches have gained traction due to their efficiency in prototyping and verification. This paper presents the design and verification of a single-cycle RISC-V core developed using a model-based design approach in the MATLAB Simulink environment. The core implements a fundamental subset of the RV32I instruction set and is converted into SystemVerilog code using HDL Coder. The generated HDL code is synthesized and tested on the Cora Z7 board, which features a Xilinx Zynq XC7Z010-1CLG400C FPGA. Verification is performed using HDL co-simulation and FPGA-in-the-Loop techniques through HDL Verifier. Test programs written in RISC-V assembly are executed, and the results are compared against the Simulink reference model, confirming functional accuracy across all stages. This work introduces a novel and fully integrated model-based methodology for RISC-V core design and hardware verification, which is not previously reported in the literature.