Damage to sub-half-micron metal-oxide-silicon field-effect transistors from plasma processing of low-k polymer interlayer dielectrics

We report on the effects of via plasma etching of low-dielectric-constant (low-k) polymers, used as interlayer dielectrics (ILDs), on the characteristics of sub-half-micron n-channel metal-oxide-silicon field-effect transistors (MOSFETs). The low-k polymers investigated are benzocylobutene and fluorinated poly-arylene-ether. The MOSFETs employed are made sensitive to via etching by incorporating an array of either 58×58 or 183×213 via holes to the gate electrode. We have found that the via etching of the polymer ILD damages the MOSFET as witnessed by the observed degradation in the transistor's parameter. The damage incurred by the MOSFET is of a charging type and is caused by plasma-induced stress current flowing into the gate oxide and oxide-Si interface through regions in the polymer ILD that are rendered leaky by the via etching plasma. We have observed that the inclusion of an insulating layer, such as Si₃N₄, can significantly inhibit the damaging effects of the via etch. Annealing at approximately 350 °C is found to eliminate the via-etch-induced damage and to improve the MOSFET's parameters.