Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools

The open RISC-V ISA has enabled rapid processor innovation, but verification remains challenging due to core-specific solutions that lack scalability. This paper introduces a reusable verification framework that combines RISCV-DV for random instruction generation with both open-source (Python flow, Spike ISS) and commercial tools (Xcelium). A custom tracer integrated into the Hornet RV32IMF core captures execution logs, which are automatically compared with Spike through structured CSV-based scripts. This approach systematically detects subtle errors often missed by directed tests, including incorrect handling of IEEE-754 rounding modes and precision loss in arithmetic units such as division and square root. The framework successfully uncovered and resolved multiple floating-point bugs in Hornet while demonstrating compatibility with both open and closed-source flows. By ensuring compliance with RISC-V and IEEE-754 standards, the proposed environment provides a scalable, flexible foundation for verifying current and future cores with advanced arithmetic capabilities.