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CMOS design of a multi-input analog multiplier

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde BölümKonferans katkısıbilirkişi

8 Atıf (Scopus)

Özet

This paper presents a new method in order to implement a high-performance CMOS multi-input analog multiplier circuit. The method is based on the effective realizations of exponential and logarithmic functions. The main advantage of this multiplier is the capability of having multiinput signals while keeping total harmonic distortion low. The circuit is designed and simulated using MATLAB software and HSPICE simulator using level 49 parameters (BSIM3v3) in 0.35μm standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 0.9%, a THD of 0.33% in 1MHz (20-A p-p), and a maximum power consumption of 0.89mW.

Orijinal dilİngilizce
Ana bilgisayar yayını başlığıPRIME 2012; 8th Conference on Ph.D. Research in Microelectronics and Electronics
YayınlayanInstitute of Electrical and Electronics Engineers Inc.
Sayfalar217-220
Sayfa sayısı4
ISBN (Elektronik)9783800734429
Yayın durumuYayınlandı - 2012
Etkinlik8th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2012 - Aachen, Germany
Süre: 12 Haz 201215 Haz 2012

Yayın serisi

AdıPRIME 2012; 8th Conference on Ph.D. Research in Microelectronics and Electronics

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???event.eventtypes.event.conference???8th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2012
Ülke/BölgeGermany
ŞehirAachen
Periyot12/06/1215/06/12

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