Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi

Oguzhan Cik; Mustak Erhan Yalcin

doi:10.1109/SIU49456.2020.9302072

Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi

Oguzhan Cik
, Mustak Erhan Yalcin

Elektronik ve Hab.Müh.Bölümü

Ulak Haberleşme A.Ş.

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

Özet

In this work, a novel digital hardware architecture is proposed in order to accelerate the packet classication functions of network router on hardware. The proposed design is implemented on FPGA. Besides, in order to obtain maximum performance, this design is optimized by using several design techniques. The proposed design has more scalable architecture than the others in literature. According the implementation and test results, the proposed design has %15 faster clock speed than similar works.

Tercüme edilen katkı başlığı	A Hardware Accelerated Packet Classifier Design for A Network Router
Orijinal dil	Türkçe
Ana bilgisayar yayını başlığı	2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings
Yayınlayan	Institute of Electrical and Electronics Engineers Inc.
ISBN (Elektronik)	9781728172064
DOI'lar	https://doi.org/10.1109/SIU49456.2020.9302072
Yayın durumu	Yayınlandı - 5 Eki 2020
Etkinlik	28th Signal Processing and Communications Applications Conference, SIU 2020 - Gaziantep, Turkey Süre: 5 Eki 2020 → 7 Eki 2020

Yayın serisi

Adı	2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	28th Signal Processing and Communications Applications Conference, SIU 2020
Ülke/Bölge	Turkey
Şehir	Gaziantep
Periyot	5/10/20 → 7/10/20

Bibliyografik not

Publisher Copyright:
© 2020 IEEE.

Keywords

AXI
CAM
FPGA
TCAM
fast lookup
hardware-software co-design
network
router

Belgeye Erişim

10.1109/SIU49456.2020.9302072

Diğer Dosyalar ve Linkler

Link to publication in Scopus

Alıntı Yap

Cik, O., & Yalcin, M. E. (2020). Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi. In 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings Makale 9302072 (2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SIU49456.2020.9302072

Cik, Oguzhan ; Yalcin, Mustak Erhan. / Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi. 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. (2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings).

@inproceedings{1f31cecdfdb64a08ab49f77c29c2928c,

title = "Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi",

abstract = "In this work, a novel digital hardware architecture is proposed in order to accelerate the packet classication functions of network router on hardware. The proposed design is implemented on FPGA. Besides, in order to obtain maximum performance, this design is optimized by using several design techniques. The proposed design has more scalable architecture than the others in literature. According the implementation and test results, the proposed design has \%15 faster clock speed than similar works.",

keywords = "AXI, CAM, FPGA, TCAM, fast lookup, hardware-software co-design, network, router",

author = "Oguzhan Cik and Yalcin, \{Mustak Erhan\}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 28th Signal Processing and Communications Applications Conference, SIU 2020 ; Conference date: 05-10-2020 Through 07-10-2020",

year = "2020",

month = oct,

day = "5",

doi = "10.1109/SIU49456.2020.9302072",

language = "T{\"u}rk{\c c}e",

series = "2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings",

address = "United States",

}

Cik, O & Yalcin, ME 2020, Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi. in 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings., 9302072, 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 28th Signal Processing and Communications Applications Conference, SIU 2020, Gaziantep, Turkey, 5/10/20. https://doi.org/10.1109/SIU49456.2020.9302072

Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi. / Cik, Oguzhan; Yalcin, Mustak Erhan.
2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9302072 (2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings).

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

TY - GEN

T1 - Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi

AU - Cik, Oguzhan

AU - Yalcin, Mustak Erhan

PY - 2020/10/5

Y1 - 2020/10/5

N2 - In this work, a novel digital hardware architecture is proposed in order to accelerate the packet classication functions of network router on hardware. The proposed design is implemented on FPGA. Besides, in order to obtain maximum performance, this design is optimized by using several design techniques. The proposed design has more scalable architecture than the others in literature. According the implementation and test results, the proposed design has %15 faster clock speed than similar works.

AB - In this work, a novel digital hardware architecture is proposed in order to accelerate the packet classication functions of network router on hardware. The proposed design is implemented on FPGA. Besides, in order to obtain maximum performance, this design is optimized by using several design techniques. The proposed design has more scalable architecture than the others in literature. According the implementation and test results, the proposed design has %15 faster clock speed than similar works.

KW - AXI

KW - CAM

KW - FPGA

KW - TCAM

KW - fast lookup

KW - hardware-software co-design

KW - network

KW - router

UR - https://www.scopus.com/pages/publications/85100303729

U2 - 10.1109/SIU49456.2020.9302072

DO - 10.1109/SIU49456.2020.9302072

M3 - Konferans katkısı

AN - SCOPUS:85100303729

T3 - 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings

BT - 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 28th Signal Processing and Communications Applications Conference, SIU 2020

Y2 - 5 October 2020 through 7 October 2020

ER -

Cik O, Yalcin ME. Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi. In 2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2020. 9302072. (2020 28th Signal Processing and Communications Applications Conference, SIU 2020 - Proceedings). doi: 10.1109/SIU49456.2020.9302072

Bir Ag Yonlendiricisi icin Donanimla Hizlandirilmis Bir Paket Siniflayici Tasarimi

Özet

Yayın serisi

???event.eventtypes.event.conference???

Bibliyografik not

Keywords

Belgeye Erişim

Diğer Dosyalar ve Linkler

Parmak izi

Alıntı Yap