An FPGA implementation of a RISC-V based SoC system for image processing applications

Erfan Gholizadehazari; Tuba Ayhan; Berna Ors

doi:10.1109/SIU53274.2021.9477998

An FPGA implementation of a RISC-V based SoC system for image processing applications

Erfan Gholizadehazari
, Tuba Ayhan
, Berna Ors

Elektronik ve Hab.Müh.Bölümü

Istanbul Technical University
MEF University

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

12 Atıf (Scopus)

Özet

The Laplacian filter is one of the fundamental applications in image processing. In our work, the Laplacian filter has been applied to an image, and both hardware and software implementation of the filter has been studied. Our system consists of an OV7670 Camera module, Nexys 4 DDR FPGA board and VGA monitor to display the processed video stream. Mentioned process has forwarding tasks: camera module captures raw RGB data and writes to RAM, Laplacian filter IP processes raw image and the results written back to memory. VGA modules show output images to monitor. The Laplacian filter part considered in hardware and software implementation is compared in terms of time and area.

Orijinal dil	İngilizce
Ana bilgisayar yayını başlığı	SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings
Yayınlayan	Institute of Electrical and Electronics Engineers Inc.
ISBN (Elektronik)	9781665436496
DOI'lar	https://doi.org/10.1109/SIU53274.2021.9477998
Yayın durumu	Yayınlandı - 9 Haz 2021
Etkinlik	29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021 - Virtual, Istanbul, Türkiye Süre: 9 Haz 2021 → 11 Haz 2021

Yayın serisi

Adı	SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021
Ülke/Bölge	Türkiye
Şehir	Virtual, Istanbul
Periyot	9/06/21 → 11/06/21

Bibliyografik not

Publisher Copyright:
© 2021 IEEE.

Belgeye Erişim

10.1109/SIU53274.2021.9477998

Diğer Dosyalar ve Linkler

Link to publication in Scopus

Alıntı Yap

Gholizadehazari, E., Ayhan, T., & Ors, B. (2021). An FPGA implementation of a RISC-V based SoC system for image processing applications. In SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings Makale 9477998 (SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SIU53274.2021.9477998

Gholizadehazari, Erfan ; Ayhan, Tuba ; Ors, Berna. / An FPGA implementation of a RISC-V based SoC system for image processing applications. SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. (SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings).

@inproceedings{b7bc09558c174a3f8c13ece9cb47ffa5,

title = "An FPGA implementation of a RISC-V based SoC system for image processing applications",

abstract = "The Laplacian filter is one of the fundamental applications in image processing. In our work, the Laplacian filter has been applied to an image, and both hardware and software implementation of the filter has been studied. Our system consists of an OV7670 Camera module, Nexys 4 DDR FPGA board and VGA monitor to display the processed video stream. Mentioned process has forwarding tasks: camera module captures raw RGB data and writes to RAM, Laplacian filter IP processes raw image and the results written back to memory. VGA modules show output images to monitor. The Laplacian filter part considered in hardware and software implementation is compared in terms of time and area.",

keywords = "Laplacian Filter, RISC-V, SoC",

author = "Erfan Gholizadehazari and Tuba Ayhan and Berna Ors",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021 ; Conference date: 09-06-2021 Through 11-06-2021",

year = "2021",

month = jun,

day = "9",

doi = "10.1109/SIU53274.2021.9477998",

language = "English",

series = "SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings",

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}

Gholizadehazari, E, Ayhan, T & Ors, B 2021, An FPGA implementation of a RISC-V based SoC system for image processing applications. in SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings., 9477998, SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings, Institute of Electrical and Electronics Engineers Inc., 29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021, Virtual, Istanbul, Türkiye, 9/06/21. https://doi.org/10.1109/SIU53274.2021.9477998

An FPGA implementation of a RISC-V based SoC system for image processing applications. / Gholizadehazari, Erfan; Ayhan, Tuba; Ors, Berna.
SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9477998 (SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings).

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

TY - GEN

T1 - An FPGA implementation of a RISC-V based SoC system for image processing applications

AU - Gholizadehazari, Erfan

AU - Ayhan, Tuba

AU - Ors, Berna

PY - 2021/6/9

Y1 - 2021/6/9

N2 - The Laplacian filter is one of the fundamental applications in image processing. In our work, the Laplacian filter has been applied to an image, and both hardware and software implementation of the filter has been studied. Our system consists of an OV7670 Camera module, Nexys 4 DDR FPGA board and VGA monitor to display the processed video stream. Mentioned process has forwarding tasks: camera module captures raw RGB data and writes to RAM, Laplacian filter IP processes raw image and the results written back to memory. VGA modules show output images to monitor. The Laplacian filter part considered in hardware and software implementation is compared in terms of time and area.

AB - The Laplacian filter is one of the fundamental applications in image processing. In our work, the Laplacian filter has been applied to an image, and both hardware and software implementation of the filter has been studied. Our system consists of an OV7670 Camera module, Nexys 4 DDR FPGA board and VGA monitor to display the processed video stream. Mentioned process has forwarding tasks: camera module captures raw RGB data and writes to RAM, Laplacian filter IP processes raw image and the results written back to memory. VGA modules show output images to monitor. The Laplacian filter part considered in hardware and software implementation is compared in terms of time and area.

KW - Laplacian Filter

KW - RISC-V

KW - SoC

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U2 - 10.1109/SIU53274.2021.9477998

DO - 10.1109/SIU53274.2021.9477998

M3 - Conference contribution

AN - SCOPUS:85111470201

T3 - SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings

BT - SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 29th IEEE Conference on Signal Processing and Communications Applications, SIU 2021

Y2 - 9 June 2021 through 11 June 2021

ER -

Gholizadehazari E, Ayhan T, Ors B. An FPGA implementation of a RISC-V based SoC system for image processing applications. In SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. 9477998. (SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings). doi: 10.1109/SIU53274.2021.9477998

An FPGA implementation of a RISC-V based SoC system for image processing applications

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Bibliyografik not

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