A rare event based yield estimation methodology for analog circuits

Izel Çaǧin Odabaşi; Mustafa Berke Yelten; Engin Afacan; Faik Baskaya; Ali Emre Pusane; Günhan Dündar

doi:10.1109/DDECS.2018.00013

A rare event based yield estimation methodology for analog circuits

Izel Çaǧin Odabaşi, Mustafa Berke Yelten, Engin Afacan, Faik Baskaya, Ali Emre Pusane, Günhan Dündar

Elektronik ve Hab.Müh.Bölümü

Araştırma sonucu: ???type-name??? › Konferans katkısı › bilirkişi

5 Atıf (Scopus)

Özet

With the growing use of analog circuits in sensor systems for internet of things applications, estimation of their yield has become critical in order to increase the efficiency of large volume manufacturing. In this paper, a methodology to estimate the yield of analog circuits beyond 95% is proposed. The methodology is based on an algorithm that uses adaptive sampling to approach the 'tail' region of the initial distribution which contains the dysfunctional units. These units do not satisfy the initial design targets thereby lowering the yield. An inverter and a two-stage operational amplifier have been used to verify the methodology where the reference distribution is based on 10⁶ samples for both circuits. Simulation results reveal that the accuracy for 95%, 98%, and 99% yield has been compromised by less than 2.1%, 5.7%, and 7.4%, respectively, whereas the computation cost is reduced by 20×.

Orijinal dil	İngilizce
Ana bilgisayar yayını başlığı	Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018
Yayınlayan	Institute of Electrical and Electronics Engineers Inc.
Sayfalar	33-38
Sayfa sayısı	6
ISBN (Elektronik)	9781538657546
DOI'lar	https://doi.org/10.1109/DDECS.2018.00013
Yayın durumu	Yayınlandı - 11 Tem 2018
Etkinlik	21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018 - Budapest, Hungary Süre: 25 Nis 2018 → 27 Nis 2018

Yayın serisi

Adı	Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018
Ülke/Bölge	Hungary
Şehir	Budapest
Periyot	25/04/18 → 27/04/18

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Publisher Copyright:
© 2018 IEEE.

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Belgeye Erişim

10.1109/DDECS.2018.00013

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Link to publication in Scopus

Alıntı Yap

Odabaşi, I. Ç., Yelten, M. B., Afacan, E., Baskaya, F., Pusane, A. E., & Dündar, G. (2018). A rare event based yield estimation methodology for analog circuits. In Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018 (pp. 33-38). (Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DDECS.2018.00013

Odabaşi, Izel Çaǧin ; Yelten, Mustafa Berke ; Afacan, Engin et al. / A rare event based yield estimation methodology for analog circuits. Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 33-38 (Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018).

@inproceedings{a72db3b4fc4645c3aa6186632d5144c4,

title = "A rare event based yield estimation methodology for analog circuits",

abstract = "With the growing use of analog circuits in sensor systems for internet of things applications, estimation of their yield has become critical in order to increase the efficiency of large volume manufacturing. In this paper, a methodology to estimate the yield of analog circuits beyond 95% is proposed. The methodology is based on an algorithm that uses adaptive sampling to approach the 'tail' region of the initial distribution which contains the dysfunctional units. These units do not satisfy the initial design targets thereby lowering the yield. An inverter and a two-stage operational amplifier have been used to verify the methodology where the reference distribution is based on 106 samples for both circuits. Simulation results reveal that the accuracy for 95%, 98%, and 99% yield has been compromised by less than 2.1%, 5.7%, and 7.4%, respectively, whereas the computation cost is reduced by 20×.",

keywords = "Analog circuits, Parametric faults, Process variations, Rare event, Yield estimation",

author = "Odaba{\c s}i, {Izel {\c C}aǧin} and Yelten, {Mustafa Berke} and Engin Afacan and Faik Baskaya and Pusane, {Ali Emre} and G{\"u}nhan D{\"u}ndar",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018 ; Conference date: 25-04-2018 Through 27-04-2018",

year = "2018",

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day = "11",

doi = "10.1109/DDECS.2018.00013",

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series = "Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018",

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Odabaşi, IÇ, Yelten, MB, Afacan, E, Baskaya, F, Pusane, AE & Dündar, G 2018, A rare event based yield estimation methodology for analog circuits. in Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018. Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018, Institute of Electrical and Electronics Engineers Inc., pp. 33-38, 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018, Budapest, Hungary, 25/04/18. https://doi.org/10.1109/DDECS.2018.00013

A rare event based yield estimation methodology for analog circuits. / Odabaşi, Izel Çaǧin; Yelten, Mustafa Berke; Afacan, Engin et al.
Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 33-38 (Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018).

Araştırma sonucu: ???type-name??? › Konferans katkısı › bilirkişi

TY - GEN

T1 - A rare event based yield estimation methodology for analog circuits

AU - Odabaşi, Izel Çaǧin

AU - Yelten, Mustafa Berke

AU - Afacan, Engin

AU - Baskaya, Faik

AU - Pusane, Ali Emre

AU - Dündar, Günhan

PY - 2018/7/11

Y1 - 2018/7/11

N2 - With the growing use of analog circuits in sensor systems for internet of things applications, estimation of their yield has become critical in order to increase the efficiency of large volume manufacturing. In this paper, a methodology to estimate the yield of analog circuits beyond 95% is proposed. The methodology is based on an algorithm that uses adaptive sampling to approach the 'tail' region of the initial distribution which contains the dysfunctional units. These units do not satisfy the initial design targets thereby lowering the yield. An inverter and a two-stage operational amplifier have been used to verify the methodology where the reference distribution is based on 106 samples for both circuits. Simulation results reveal that the accuracy for 95%, 98%, and 99% yield has been compromised by less than 2.1%, 5.7%, and 7.4%, respectively, whereas the computation cost is reduced by 20×.

AB - With the growing use of analog circuits in sensor systems for internet of things applications, estimation of their yield has become critical in order to increase the efficiency of large volume manufacturing. In this paper, a methodology to estimate the yield of analog circuits beyond 95% is proposed. The methodology is based on an algorithm that uses adaptive sampling to approach the 'tail' region of the initial distribution which contains the dysfunctional units. These units do not satisfy the initial design targets thereby lowering the yield. An inverter and a two-stage operational amplifier have been used to verify the methodology where the reference distribution is based on 106 samples for both circuits. Simulation results reveal that the accuracy for 95%, 98%, and 99% yield has been compromised by less than 2.1%, 5.7%, and 7.4%, respectively, whereas the computation cost is reduced by 20×.

KW - Analog circuits

KW - Parametric faults

KW - Process variations

KW - Rare event

KW - Yield estimation

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SP - 33

EP - 38

BT - Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018

Y2 - 25 April 2018 through 27 April 2018

ER -

Odabaşi IÇ, Yelten MB, Afacan E, Baskaya F, Pusane AE, Dündar G. A rare event based yield estimation methodology for analog circuits. In Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 33-38. (Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018). doi: 10.1109/DDECS.2018.00013

A rare event based yield estimation methodology for analog circuits

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