A new neuron model suitable for low power VLSI implementation

Ozgur Erdener; Serdar Ozoguz

doi:10.1109/ELECO.2015.7394550

A new neuron model suitable for low power VLSI implementation

Ozgur Erdener
, Serdar Ozoguz

Elektronik ve Hab.Müh.Bölümü

Istanbul Technical University

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

Özet

This paper presents a new dynamical neuron model which is appropriate for electronic circuit implementation and its low power, compact VLSI implementation. The neuron circuit consists of one first-order log domain filters, hyperbolic type nonlinear function generator and resetting circuitry. Owing to the log domain design and current-mode operation in a 0.35 μm CMOS process, the circuit occupies low chip area and has very low power consumption during real time scale operation. These features make the circuit suitable for hybrid interface applications and large scale VLSI neuromorphic networks.

Orijinal dil	İngilizce
Ana bilgisayar yayını başlığı	ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering
Yayınlayan	Institute of Electrical and Electronics Engineers Inc.
Sayfalar	15-19
Sayfa sayısı	5
ISBN (Elektronik)	9786050107371
DOI'lar	https://doi.org/10.1109/ELECO.2015.7394550
Yayın durumu	Yayınlandı - 28 Oca 2016
Etkinlik	9th International Conference on Electrical and Electronics Engineering, ELECO 2015 - Bursa, Türkiye Süre: 26 Kas 2015 → 28 Kas 2015

Yayın serisi

Adı	ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	9th International Conference on Electrical and Electronics Engineering, ELECO 2015
Ülke/Bölge	Türkiye
Şehir	Bursa
Periyot	26/11/15 → 28/11/15

Bibliyografik not

Publisher Copyright:
© 2015 Chamber of Electrical Engineers of Turkey.

Belgeye Erişim

10.1109/ELECO.2015.7394550

Diğer Dosyalar ve Linkler

Link to publication in Scopus

Alıntı Yap

Erdener, O., & Ozoguz, S. (2016). A new neuron model suitable for low power VLSI implementation. In ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering (pp. 15-19). Makale 7394550 (ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ELECO.2015.7394550

@inproceedings{a58074e14b314792939f3544b2771ebe,

title = "A new neuron model suitable for low power VLSI implementation",

abstract = "This paper presents a new dynamical neuron model which is appropriate for electronic circuit implementation and its low power, compact VLSI implementation. The neuron circuit consists of one first-order log domain filters, hyperbolic type nonlinear function generator and resetting circuitry. Owing to the log domain design and current-mode operation in a 0.35 μm CMOS process, the circuit occupies low chip area and has very low power consumption during real time scale operation. These features make the circuit suitable for hybrid interface applications and large scale VLSI neuromorphic networks.",

author = "Ozgur Erdener and Serdar Ozoguz",

note = "Publisher Copyright: {\textcopyright} 2015 Chamber of Electrical Engineers of Turkey.; 9th International Conference on Electrical and Electronics Engineering, ELECO 2015 ; Conference date: 26-11-2015 Through 28-11-2015",

year = "2016",

month = jan,

day = "28",

doi = "10.1109/ELECO.2015.7394550",

language = "English",

series = "ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "15--19",

booktitle = "ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering",

address = "United States",

}

Erdener, O & Ozoguz, S 2016, A new neuron model suitable for low power VLSI implementation. in ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering., 7394550, ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering, Institute of Electrical and Electronics Engineers Inc., pp. 15-19, 9th International Conference on Electrical and Electronics Engineering, ELECO 2015, Bursa, Türkiye, 26/11/15. https://doi.org/10.1109/ELECO.2015.7394550

A new neuron model suitable for low power VLSI implementation. / Erdener, Ozgur; Ozoguz, Serdar.
ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering. Institute of Electrical and Electronics Engineers Inc., 2016. p. 15-19 7394550 (ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering).

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

TY - GEN

T1 - A new neuron model suitable for low power VLSI implementation

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AU - Ozoguz, Serdar

PY - 2016/1/28

Y1 - 2016/1/28

N2 - This paper presents a new dynamical neuron model which is appropriate for electronic circuit implementation and its low power, compact VLSI implementation. The neuron circuit consists of one first-order log domain filters, hyperbolic type nonlinear function generator and resetting circuitry. Owing to the log domain design and current-mode operation in a 0.35 μm CMOS process, the circuit occupies low chip area and has very low power consumption during real time scale operation. These features make the circuit suitable for hybrid interface applications and large scale VLSI neuromorphic networks.

AB - This paper presents a new dynamical neuron model which is appropriate for electronic circuit implementation and its low power, compact VLSI implementation. The neuron circuit consists of one first-order log domain filters, hyperbolic type nonlinear function generator and resetting circuitry. Owing to the log domain design and current-mode operation in a 0.35 μm CMOS process, the circuit occupies low chip area and has very low power consumption during real time scale operation. These features make the circuit suitable for hybrid interface applications and large scale VLSI neuromorphic networks.

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U2 - 10.1109/ELECO.2015.7394550

DO - 10.1109/ELECO.2015.7394550

M3 - Conference contribution

AN - SCOPUS:84963815767

T3 - ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering

SP - 15

EP - 19

BT - ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 9th International Conference on Electrical and Electronics Engineering, ELECO 2015

Y2 - 26 November 2015 through 28 November 2015

ER -

Erdener O, Ozoguz S. A new neuron model suitable for low power VLSI implementation. In ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering. Institute of Electrical and Electronics Engineers Inc. 2016. p. 15-19. 7394550. (ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering). doi: 10.1109/ELECO.2015.7394550

A new neuron model suitable for low power VLSI implementation

Özet

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Bibliyografik not

Belgeye Erişim

Diğer Dosyalar ve Linkler

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