A new neuron model suitable for low power VLSI implementation

Ozgur Erdener, Serdar Ozoguz

Araştırma sonucu: ???type-name???Konferans katkısıbilirkişi

Özet

This paper presents a new dynamical neuron model which is appropriate for electronic circuit implementation and its low power, compact VLSI implementation. The neuron circuit consists of one first-order log domain filters, hyperbolic type nonlinear function generator and resetting circuitry. Owing to the log domain design and current-mode operation in a 0.35 μm CMOS process, the circuit occupies low chip area and has very low power consumption during real time scale operation. These features make the circuit suitable for hybrid interface applications and large scale VLSI neuromorphic networks.

Orijinal dilİngilizce
Ana bilgisayar yayını başlığıELECO 2015 - 9th International Conference on Electrical and Electronics Engineering
YayınlayanInstitute of Electrical and Electronics Engineers Inc.
Sayfalar15-19
Sayfa sayısı5
ISBN (Elektronik)9786050107371
DOI'lar
Yayın durumuYayınlandı - 28 Oca 2016
Etkinlik9th International Conference on Electrical and Electronics Engineering, ELECO 2015 - Bursa, Turkey
Süre: 26 Kas 201528 Kas 2015

Yayın serisi

AdıELECO 2015 - 9th International Conference on Electrical and Electronics Engineering

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???9th International Conference on Electrical and Electronics Engineering, ELECO 2015
Ülke/BölgeTurkey
ŞehirBursa
Periyot26/11/1528/11/15

Bibliyografik not

Publisher Copyright:
© 2015 Chamber of Electrical Engineers of Turkey.

Parmak izi

A new neuron model suitable for low power VLSI implementation' araştırma başlıklarına git. Birlikte benzersiz bir parmak izi oluştururlar.

Alıntı Yap