A new implementation of fully programmable complete CNN processor core on FPGA

In this paper, a new Cellular Neural Network (CNN) processing core architecture for digital emulation of discrete time CNN is proposed. The introduced CNN core processor is capable of executing 3 × 3 template operation which is considered as instruction. The instruction performs on input and initial images where are stored on DDR RAM. A result of the instruction can be stored at different memory segments. Data transfer mechanism between DDR memory and CNN Core is design to have maximum throughput. The architecture has been combined the core unit with camera and camera control units. CNN Processor can process up to 1600 × 900 video @15 fps. System performance is depend on iteration count n which can be also defined in the instruction. Furthermore, FPGA implementation of CNN processor core with camera control units is given and the introduced system is experimentally confirmed on Spartan 6 XC6SLX45 FPGA.