A Model Based Hardware Implementation of Traffic Regulator in ARINC-664 End System

Keyphrases

• Hardware Implementation 100%
• ARINC 100%
• Traffic Regulator 100%
• End System 100%
• Bounded Delay 40%
• Convertibility 40%
• Performance Analysis 20%
• Scheduling Algorithm 20%
• Data Transfer 20%
• Simulation Environment 20%
• Low Latency 20%
• Low Power Consumption 20%
• Data Security 20%
• Communication Protocol 20%
• Testing Environment 20%
• Simulink 20%
• Hardware Design 20%
• Shaping Mechanism 20%
• Rapid Prototyping 20%
• Hardware Description Language 20%
• Ethernet 20%
• Ethernet Frame 20%
• Redundant Communications 20%
• Traffic Scheduling 20%
• Deterministic Network 20%
• Jitter 20%
• Traffic Shaping 20%
• Scheduling Mechanism 20%
• Fast Testing 20%
• Dynamic Traffic 20%
• Avionics Applications 20%

Computer Science

• Hardware Implementation 100%
• Field Programmable Gate Arrays 100%
• Scheduling Algorithm 50%
• Simulation Environment 50%
• Avionics 50%
• Dynamic Traffic 50%
• Hardware Design 50%
• Network Protocols 50%
• Deterministic Network 50%
• Implementation Choice 50%
• Scheduling Mechanism 50%
• Testing Environment 50%
• Low Power Consumption 50%
• Performance Analysis 50%
• Ethernet Frame 50%
• Computer Hardware 50%
• Hardware Description Languages 50%

Engineering

• Field Programmable Gate Arrays 100%
• End System 100%
• Performance Analysis 50%
• Avionics 50%
• Data Transfer 50%
• Specifies 50%
• Low Power Consumption 50%
• Fast Prototyping 50%
• Ethernet Frame 50%
• Simulation Environment 50%
• Data Security 50%