TY - GEN
T1 - A low power VLSI implementation of the Izhikevich neuron model
AU - Demirkol, A. Samil
AU - Ozoguz, Serdar
PY - 2011
Y1 - 2011
N2 - We present a low-power VLSI implementation of the Izhikevich neuron model utilizing two first-order log-domain filters as the main building block. One of the filters includes an active diode connection in order to lower current levels to obtain a low-power, large time constant design. Thus, the neuron circuit operates in sub-threshold regime with biological time scale. The possible applications of the presented implementation are simulating large scale VLSI neural networks and building hybrid interface systems. The simulation results demonstrate the success of replicating the firing patterns of real neurons.
AB - We present a low-power VLSI implementation of the Izhikevich neuron model utilizing two first-order log-domain filters as the main building block. One of the filters includes an active diode connection in order to lower current levels to obtain a low-power, large time constant design. Thus, the neuron circuit operates in sub-threshold regime with biological time scale. The possible applications of the presented implementation are simulating large scale VLSI neural networks and building hybrid interface systems. The simulation results demonstrate the success of replicating the firing patterns of real neurons.
UR - https://www.scopus.com/pages/publications/80052537714
U2 - 10.1109/NEWCAS.2011.5981282
DO - 10.1109/NEWCAS.2011.5981282
M3 - Conference contribution
AN - SCOPUS:80052537714
SN - 9781612841359
T3 - 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011
SP - 169
EP - 172
BT - 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011
T2 - 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011
Y2 - 26 June 2011 through 29 June 2011
ER -