A layered UVM based testbench design for SpaceWire

Ahmet Çaǧri Baǧbaba; Buse Ustaoǧlu; Inan Erdem; Berna Ors

doi:10.1109/ELECO.2015.7394599

A layered UVM based testbench design for SpaceWire

Ahmet Çaǧri Baǧbaba
, Buse Ustaoǧlu
, Inan Erdem
, Berna Ors

Elektronik ve Hab.Müh.Bölümü

Istanbul Technical University
Anka Mikroelektronik Sistemler

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

3 Atıf (Scopus)

Özet

The Universal Verification Methodology is a standard which is designed to enable creation of reusable, robust and interoperable verification IP and testbench components. In this work, we implemented layered UVM testbench for SpaceWire which is a spacecraft communication network based in part on the IEEE 1355 standard of communications. This design helps further analyzes of SpaceWire by testing different SpaceWire layers such as exchange layer and character layer. Transactions were used at all layer of protocol and user can make analysis, coverage collecting and debugging through this design. In the conclusion, all simulator results and details about Verification IP design were given.

Orijinal dil	İngilizce
Ana bilgisayar yayını başlığı	ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering
Yayınlayan	Institute of Electrical and Electronics Engineers Inc.
Sayfalar	1164-1168
Sayfa sayısı	5
ISBN (Elektronik)	9786050107371
DOI'lar	https://doi.org/10.1109/ELECO.2015.7394599
Yayın durumu	Yayınlandı - 28 Oca 2016
Etkinlik	9th International Conference on Electrical and Electronics Engineering, ELECO 2015 - Bursa, Türkiye Süre: 26 Kas 2015 → 28 Kas 2015

Yayın serisi

Adı	ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	9th International Conference on Electrical and Electronics Engineering, ELECO 2015
Ülke/Bölge	Türkiye
Şehir	Bursa
Periyot	26/11/15 → 28/11/15

Bibliyografik not

Publisher Copyright:
© 2015 Chamber of Electrical Engineers of Turkey.

Belgeye Erişim

10.1109/ELECO.2015.7394599

Diğer Dosyalar ve Linkler

Link to publication in Scopus

Alıntı Yap

Baǧbaba, A. Ç., Ustaoǧlu, B., Erdem, I., & Ors, B. (2016). A layered UVM based testbench design for SpaceWire. In ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering (pp. 1164-1168). Makale 7394599 (ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ELECO.2015.7394599

@inproceedings{7a30b422c5624ec9b4a05427995dfa02,

title = "A layered UVM based testbench design for SpaceWire",

abstract = "The Universal Verification Methodology is a standard which is designed to enable creation of reusable, robust and interoperable verification IP and testbench components. In this work, we implemented layered UVM testbench for SpaceWire which is a spacecraft communication network based in part on the IEEE 1355 standard of communications. This design helps further analyzes of SpaceWire by testing different SpaceWire layers such as exchange layer and character layer. Transactions were used at all layer of protocol and user can make analysis, coverage collecting and debugging through this design. In the conclusion, all simulator results and details about Verification IP design were given.",

author = "Baǧbaba, \{Ahmet {\c C}aǧri\} and Buse Ustaoǧlu and Inan Erdem and Berna Ors",

note = "Publisher Copyright: {\textcopyright} 2015 Chamber of Electrical Engineers of Turkey.; 9th International Conference on Electrical and Electronics Engineering, ELECO 2015 ; Conference date: 26-11-2015 Through 28-11-2015",

year = "2016",

month = jan,

day = "28",

doi = "10.1109/ELECO.2015.7394599",

language = "English",

series = "ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1164--1168",

booktitle = "ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering",

address = "United States",

}

Baǧbaba, AÇ, Ustaoǧlu, B, Erdem, I & Ors, B 2016, A layered UVM based testbench design for SpaceWire. in ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering., 7394599, ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering, Institute of Electrical and Electronics Engineers Inc., pp. 1164-1168, 9th International Conference on Electrical and Electronics Engineering, ELECO 2015, Bursa, Türkiye, 26/11/15. https://doi.org/10.1109/ELECO.2015.7394599

A layered UVM based testbench design for SpaceWire. / Baǧbaba, Ahmet Çaǧri; Ustaoǧlu, Buse; Erdem, Inan et al.
ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering. Institute of Electrical and Electronics Engineers Inc., 2016. p. 1164-1168 7394599 (ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering).

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

TY - GEN

T1 - A layered UVM based testbench design for SpaceWire

AU - Baǧbaba, Ahmet Çaǧri

AU - Ustaoǧlu, Buse

AU - Erdem, Inan

AU - Ors, Berna

PY - 2016/1/28

Y1 - 2016/1/28

N2 - The Universal Verification Methodology is a standard which is designed to enable creation of reusable, robust and interoperable verification IP and testbench components. In this work, we implemented layered UVM testbench for SpaceWire which is a spacecraft communication network based in part on the IEEE 1355 standard of communications. This design helps further analyzes of SpaceWire by testing different SpaceWire layers such as exchange layer and character layer. Transactions were used at all layer of protocol and user can make analysis, coverage collecting and debugging through this design. In the conclusion, all simulator results and details about Verification IP design were given.

AB - The Universal Verification Methodology is a standard which is designed to enable creation of reusable, robust and interoperable verification IP and testbench components. In this work, we implemented layered UVM testbench for SpaceWire which is a spacecraft communication network based in part on the IEEE 1355 standard of communications. This design helps further analyzes of SpaceWire by testing different SpaceWire layers such as exchange layer and character layer. Transactions were used at all layer of protocol and user can make analysis, coverage collecting and debugging through this design. In the conclusion, all simulator results and details about Verification IP design were given.

UR - https://www.scopus.com/pages/publications/84963930462

U2 - 10.1109/ELECO.2015.7394599

DO - 10.1109/ELECO.2015.7394599

M3 - Conference contribution

AN - SCOPUS:84963930462

T3 - ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering

SP - 1164

EP - 1168

BT - ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 9th International Conference on Electrical and Electronics Engineering, ELECO 2015

Y2 - 26 November 2015 through 28 November 2015

ER -

Baǧbaba AÇ, Ustaoǧlu B, Erdem I, Ors B. A layered UVM based testbench design for SpaceWire. In ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering. Institute of Electrical and Electronics Engineers Inc. 2016. p. 1164-1168. 7394599. (ELECO 2015 - 9th International Conference on Electrical and Electronics Engineering). doi: 10.1109/ELECO.2015.7394599

A layered UVM based testbench design for SpaceWire

Özet

Yayın serisi

???event.eventtypes.event.conference???

Bibliyografik not

Belgeye Erişim

Diğer Dosyalar ve Linkler

Parmak izi

Alıntı Yap