A highly-linear, sub-mW LNA at 2.4 GHz in 40 nm CMOS process

Didem Erol As, Mustafa Berke Yelten*

*Bu çalışma için yazışmadan sorumlu yazar

Araştırma sonucu: ???type-name???Makalebilirkişi

Özet

This paper focuses on designing low-power, low-noise amplifiers (LNA) performances. Different LNA topologies operating with sub-mW power consumption at 2.4 GHz have been implemented in a commercial 40 nm CMOS process. The LNA1 (cascode common source LNA) has a voltage gain of 12.22 dB, a noise figure (NF) of 4.35 dB, and a third-order input intercept point (IIP3) of −12.68 dBm at 995.6 μW while the proposed LNA2 with improved linearity has a 5.68 dB gain, 5.13 dB NF, and a −0.12 dBm IIP3. The difference between both final designs, which consist of improved linearity and gain, stems from the location of the gate inductance (Lg) in the chip. The proposed LNA3 with an on-chip Lg has a voltage gain of 11.1 dB, an NF of 4.27 dB, and an IIP3 of -0.82 dBm. Moreover, the proposed LNA4 with an off-chip Lg has 10.31 dB voltage gain, 3.68 dB NF, and 0.89 dBm IIP3 at 989.6 μW in post-layout simulations. Comparing the LNAs, the proposed LNA4 with an off-chip Lg has the best figure-of-merit (FOM). This work aims to achieve improved linearity figures at sub-mW power.

Orijinal dilİngilizce
Sayfa (başlangıç-bitiş)278-285
Sayfa sayısı8
DergiIntegration
Hacim88
DOI'lar
Yayın durumuYayınlandı - Oca 2023

Bibliyografik not

Publisher Copyright:
© 2022 Elsevier B.V.

Finansman

This work was sponsored by the Scientific and Technological Research Council of Turkey under the project TÜBİTAK 1001 118E253 .

FinansörlerFinansör numarası
Türkiye Bilimsel ve Teknolojik Araştırma Kurumu1001 118E253

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