Özet
Using discrete wavelet transform (DWT) in highspeed signal processing applications imposes a high degree of care to hardware resource availability, latency and power consumption. In this paper, we investigate the design and implementation aspects of 1-level DWT by employing a finite impulse response (FIR) filter on FPGA platform. FPGAs come with a limited number of multipliers, which restricts the size and number of DWT levels. As a result, a multiplication-free architecture becomes a necessity for implementing large DWT. Our goal is to estimate the performance requirements and hardware resources for two key multiplication-free architectures, namely, distributed arithmetic algorithm (DAA) and residue number system (RNS), allowing for selection of the proper algorithm and implementation of DAA and RNS-based DWT. The design has been implemented and synthesized in Xilinx Virtex-6 ML605 FPGA, taking advantage of Virtex-6's embedded block RAMs (BRAMs). The results show that the DAA-based approach is appropriate and feasible for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps.
Orijinal dil | İngilizce |
---|---|
Ana bilgisayar yayını başlığı | Proceedings of 2017 International Conference on Engineering and Technology, ICET 2017 |
Yayınlayan | Institute of Electrical and Electronics Engineers Inc. |
Sayfalar | 1-6 |
Sayfa sayısı | 6 |
ISBN (Elektronik) | 9781538619490 |
DOI'lar | |
Yayın durumu | Yayınlandı - 2 Tem 2017 |
Etkinlik | 2017 International Conference on Engineering and Technology, ICET 2017 - Antalya, Turkey Süre: 21 Ağu 2017 → 23 Ağu 2017 |
Yayın serisi
Adı | Proceedings of 2017 International Conference on Engineering and Technology, ICET 2017 |
---|---|
Hacim | 2018-January |
???event.eventtypes.event.conference???
???event.eventtypes.event.conference??? | 2017 International Conference on Engineering and Technology, ICET 2017 |
---|---|
Ülke/Bölge | Turkey |
Şehir | Antalya |
Periyot | 21/08/17 → 23/08/17 |
Bibliyografik not
Publisher Copyright:© 2017 IEEE.