A 200 GHz Bow-Tie Antenna Employing Frequency Selective Surface Integration for On-Chip Systems

This study presents an on-chip bow-tie antenna miniaturized to approximately 200 GHz with an impedance bandwidth of roughly 20 GHz at -10 dB. The antenna is designed in a standard 0.18 μm CMOS process as a CPS-fed radiator, together with an FSS-inspired element. The bow-tie radiator is realized in the top metal layer, while the bottom metal layer is divided into a grid of sub-wavelength copper cells. Compared to the reference design, the proposed antenna shifts the optimal performance to 200 GHz, achieves a return loss of about 26 dB over a 20 GHz bandwidth, and improves the peak realized gain to nearly 3.0 dBi. The antenna exhibits total and radiation efficiencies of 95 % and 97 %, respectively.