A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs

Hakan Cetinkaya; Ali Zeki; Alper Girgin; Enver Derun Karabeyoglu; Tufan Coskun Karalar

doi:10.1109/ICECS.2018.8618005

A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs

Hakan Cetinkaya
, Ali Zeki
, Alper Girgin
, Enver Derun Karabeyoglu
, Tufan Coskun Karalar

Elektronik ve Hab.Müh.Bölümü

Istanbul Technical University
University of Girne

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

7 Atıf (Scopus)

Özet

This work presents a 1.6 GHz non-overlap clock generation architecture with a differential clock driver and clock level shifters for GS/s sampling rate pipeline ADCs. The clock generation system, itself, achieves SNR_jitter 10 bit ENOB at 1.6 GHz clock signal. The design, totally, consuming 16.5 mA at an external supply of 3.3 V, and, occupying 400 μm × 360 μ m silicon area, is realized in a SiGe BiCMOS 0.13 μ m process.

Orijinal dil	İngilizce
Ana bilgisayar yayını başlığı	2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
Yayınlayan	Institute of Electrical and Electronics Engineers Inc.
Sayfalar	277-280
Sayfa sayısı	4
ISBN (Elektronik)	9781538695623
DOI'lar	https://doi.org/10.1109/ICECS.2018.8618005
Yayın durumu	Yayınlandı - 2 Tem 2018
Etkinlik	25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 - Bordeaux, France Süre: 9 Ara 2018 → 12 Ara 2018

Yayın serisi

Adı	2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
Ülke/Bölge	France
Şehir	Bordeaux
Periyot	9/12/18 → 12/12/18

Bibliyografik not

Publisher Copyright:
© 2018 IEEE.

Finansman

This work is financially supported by the Scientific and Technological Research Council of Turkey (TÜBİTAK) for the partial fulfilment of the project, TÜBİTAK-1003, 115E752. ACKNOWLEDGMENT This work is financially supported by the Scientific and Technological Research Council of Turkey (TÜBİTAK) for the partial fulfilment of the project TÜBİTAK-1003, 115E752.

Finansörler	Finansör numarası
Scientific and Technological Research Council of Turkey	TÜBİTAK-1003, 115E752
National Council for Scientific Research	TÜBİTAK-1003, 115E752

Belgeye Erişim

10.1109/ICECS.2018.8618005

Diğer Dosyalar ve Linkler

Link to publication in Scopus

Alıntı Yap

Cetinkaya, H., Zeki, A., Girgin, A., Karabeyoglu, E. D., & Karalar, T. C. (2018). A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. In 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 (pp. 277-280). Makale 8618005 (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2018.8618005

Cetinkaya, Hakan ; Zeki, Ali ; Girgin, Alper et al. / A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 277-280 (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018).

@inproceedings{dd3606beb8e04292a0294c45e810198e,

title = "A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs",

abstract = "This work presents a 1.6 GHz non-overlap clock generation architecture with a differential clock driver and clock level shifters for GS/s sampling rate pipeline ADCs. The clock generation system, itself, achieves SNRjitter 10 bit ENOB at 1.6 GHz clock signal. The design, totally, consuming 16.5 mA at an external supply of 3.3 V, and, occupying 400 μm × 360 μ m silicon area, is realized in a SiGe BiCMOS 0.13 μ m process.",

keywords = "LDOs, Non-overlap clock generation, clock level shifter, differential to single ended converter",

author = "Hakan Cetinkaya and Ali Zeki and Alper Girgin and Karabeyoglu, \{Enver Derun\} and Karalar, \{Tufan Coskun\}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 ; Conference date: 09-12-2018 Through 12-12-2018",

year = "2018",

month = jul,

day = "2",

doi = "10.1109/ICECS.2018.8618005",

language = "English",

series = "2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "277--280",

booktitle = "2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018",

address = "United States",

}

Cetinkaya, H, Zeki, A, Girgin, A, Karabeyoglu, ED & Karalar, TC 2018, A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. in 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018., 8618005, 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, Institute of Electrical and Electronics Engineers Inc., pp. 277-280, 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, Bordeaux, France, 9/12/18. https://doi.org/10.1109/ICECS.2018.8618005

A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. / Cetinkaya, Hakan; Zeki, Ali; Girgin, Alper et al.
2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 277-280 8618005 (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018).

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

TY - GEN

T1 - A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs

AU - Cetinkaya, Hakan

AU - Zeki, Ali

AU - Girgin, Alper

AU - Karabeyoglu, Enver Derun

AU - Karalar, Tufan Coskun

PY - 2018/7/2

Y1 - 2018/7/2

N2 - This work presents a 1.6 GHz non-overlap clock generation architecture with a differential clock driver and clock level shifters for GS/s sampling rate pipeline ADCs. The clock generation system, itself, achieves SNRjitter 10 bit ENOB at 1.6 GHz clock signal. The design, totally, consuming 16.5 mA at an external supply of 3.3 V, and, occupying 400 μm × 360 μ m silicon area, is realized in a SiGe BiCMOS 0.13 μ m process.

AB - This work presents a 1.6 GHz non-overlap clock generation architecture with a differential clock driver and clock level shifters for GS/s sampling rate pipeline ADCs. The clock generation system, itself, achieves SNRjitter 10 bit ENOB at 1.6 GHz clock signal. The design, totally, consuming 16.5 mA at an external supply of 3.3 V, and, occupying 400 μm × 360 μ m silicon area, is realized in a SiGe BiCMOS 0.13 μ m process.

KW - LDOs

KW - Non-overlap clock generation

KW - clock level shifter

KW - differential to single ended converter

UR - https://www.scopus.com/pages/publications/85062259603

U2 - 10.1109/ICECS.2018.8618005

DO - 10.1109/ICECS.2018.8618005

M3 - Conference contribution

AN - SCOPUS:85062259603

T3 - 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018

SP - 277

EP - 280

BT - 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018

Y2 - 9 December 2018 through 12 December 2018

ER -

Cetinkaya H, Zeki A, Girgin A, Karabeyoglu ED, Karalar TC. A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. In 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 277-280. 8618005. (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018). doi: 10.1109/ICECS.2018.8618005

A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs

Özet

Yayın serisi

???event.eventtypes.event.conference???

Bibliyografik not

Finansman

Belgeye Erişim

Diğer Dosyalar ve Linkler

Parmak izi

Alıntı Yap