10-bit High-speed CMOS comparator with offset cancellation technique

Lida Kouhalvandi; Sercan Aygun; Gokhan Gunes Ozdemir; Ece Olcay Gunes

doi:10.1109/AIEEE.2017.8270524

10-bit High-speed CMOS comparator with offset cancellation technique

Lida Kouhalvandi, Sercan Aygun, Gokhan Gunes Ozdemir, Ece Olcay Gunes

Elektronik ve Hab.Müh.Bölümü

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

4 Atıf (Scopus)

Özet

Nowadays, in all modern electronic devices a low voltage with high speed comparator plays an important role in overall performance of the systems. This paper describes the implementation of a high-speed comparator with high-resolution, 10-bit, in 0.18pM CMOS technology drawn from a 1.8 V supply which is suitable for analog-to-digital converter (ADC) applications and for electronic industry. An offset cancellation technique is done and tested in order to decrease the offset and kickback noise. Regarding the Monte Carlo and corner simulation results for 100 samples and 9 corners respectively, it can be observed that bit error rate is approximately zero and comparator can response fast to the input signals. After accessing acceptable simulation results from designed comparator, the layout of each comparator components such as Op-amps, switches, and latch have been drawn and tested in Cadence Spectre Circuit Simulator.

Orijinal dil	İngilizce
Ana bilgisayar yayını başlığı	Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017
Editörler	Andrejs Romanovs, Dalius Navakauskas, Armands Senfelds
Yayınlayan	Institute of Electrical and Electronics Engineers Inc.
Sayfalar	1-4
Sayfa sayısı	4
ISBN (Elektronik)	9781538641378
DOI'lar	https://doi.org/10.1109/AIEEE.2017.8270524
Yayın durumu	Yayınlandı - 2 Tem 2017
Etkinlik	5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017 - Riga, Latvia Süre: 24 Kas 2017 → 25 Kas 2017

Yayın serisi

Adı	Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017
Hacim	2018-January

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017
Ülke/Bölge	Latvia
Şehir	Riga
Periyot	24/11/17 → 25/11/17

Bibliyografik not

Publisher Copyright:
© 2017 IEEE.

Belgeye Erişim

10.1109/AIEEE.2017.8270524

Diğer Dosyalar ve Linkler

Link to publication in Scopus

Alıntı Yap

Kouhalvandi, L., Aygun, S., Ozdemir, G. G., & Gunes, E. O. (2017). 10-bit High-speed CMOS comparator with offset cancellation technique. In A. Romanovs, D. Navakauskas, & A. Senfelds (Eds.), Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017 (pp. 1-4). (Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017; Hac. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/AIEEE.2017.8270524

Kouhalvandi, Lida ; Aygun, Sercan ; Ozdemir, Gokhan Gunes et al. / 10-bit High-speed CMOS comparator with offset cancellation technique. Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017. editör / Andrejs Romanovs ; Dalius Navakauskas ; Armands Senfelds. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 1-4 (Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017).

@inproceedings{dc9452286a444470b7419f0db91a4776,

title = "10-bit High-speed CMOS comparator with offset cancellation technique",

abstract = "Nowadays, in all modern electronic devices a low voltage with high speed comparator plays an important role in overall performance of the systems. This paper describes the implementation of a high-speed comparator with high-resolution, 10-bit, in 0.18pM CMOS technology drawn from a 1.8 V supply which is suitable for analog-to-digital converter (ADC) applications and for electronic industry. An offset cancellation technique is done and tested in order to decrease the offset and kickback noise. Regarding the Monte Carlo and corner simulation results for 100 samples and 9 corners respectively, it can be observed that bit error rate is approximately zero and comparator can response fast to the input signals. After accessing acceptable simulation results from designed comparator, the layout of each comparator components such as Op-amps, switches, and latch have been drawn and tested in Cadence Spectre Circuit Simulator.",

keywords = "high-speed comparator, latch, layout, Monte Carlo analysis, offset cancellation, op-amp, resolution",

author = "Lida Kouhalvandi and Sercan Aygun and Ozdemir, {Gokhan Gunes} and Gunes, {Ece Olcay}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017 ; Conference date: 24-11-2017 Through 25-11-2017",

year = "2017",

month = jul,

day = "2",

doi = "10.1109/AIEEE.2017.8270524",

language = "English",

series = "Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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}

Kouhalvandi, L, Aygun, S, Ozdemir, GG & Gunes, EO 2017, 10-bit High-speed CMOS comparator with offset cancellation technique. in A Romanovs, D Navakauskas & A Senfelds (eds), Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017. Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017, hac. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017, Riga, Latvia, 24/11/17. https://doi.org/10.1109/AIEEE.2017.8270524

10-bit High-speed CMOS comparator with offset cancellation technique. / Kouhalvandi, Lida; Aygun, Sercan; Ozdemir, Gokhan Gunes et al.
Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017. ed. / Andrejs Romanovs; Dalius Navakauskas; Armands Senfelds. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-4 (Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017; Hac. 2018-January).

Araştırma sonucu: Kitap/Rapor/Konferans Bildirisinde Bölüm › Konferans katkısı › bilirkişi

TY - GEN

T1 - 10-bit High-speed CMOS comparator with offset cancellation technique

AU - Kouhalvandi, Lida

AU - Aygun, Sercan

AU - Ozdemir, Gokhan Gunes

AU - Gunes, Ece Olcay

PY - 2017/7/2

Y1 - 2017/7/2

N2 - Nowadays, in all modern electronic devices a low voltage with high speed comparator plays an important role in overall performance of the systems. This paper describes the implementation of a high-speed comparator with high-resolution, 10-bit, in 0.18pM CMOS technology drawn from a 1.8 V supply which is suitable for analog-to-digital converter (ADC) applications and for electronic industry. An offset cancellation technique is done and tested in order to decrease the offset and kickback noise. Regarding the Monte Carlo and corner simulation results for 100 samples and 9 corners respectively, it can be observed that bit error rate is approximately zero and comparator can response fast to the input signals. After accessing acceptable simulation results from designed comparator, the layout of each comparator components such as Op-amps, switches, and latch have been drawn and tested in Cadence Spectre Circuit Simulator.

AB - Nowadays, in all modern electronic devices a low voltage with high speed comparator plays an important role in overall performance of the systems. This paper describes the implementation of a high-speed comparator with high-resolution, 10-bit, in 0.18pM CMOS technology drawn from a 1.8 V supply which is suitable for analog-to-digital converter (ADC) applications and for electronic industry. An offset cancellation technique is done and tested in order to decrease the offset and kickback noise. Regarding the Monte Carlo and corner simulation results for 100 samples and 9 corners respectively, it can be observed that bit error rate is approximately zero and comparator can response fast to the input signals. After accessing acceptable simulation results from designed comparator, the layout of each comparator components such as Op-amps, switches, and latch have been drawn and tested in Cadence Spectre Circuit Simulator.

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KW - offset cancellation

KW - op-amp

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T3 - Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017

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BT - Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017

A2 - Romanovs, Andrejs

A2 - Navakauskas, Dalius

A2 - Senfelds, Armands

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017

Y2 - 24 November 2017 through 25 November 2017

ER -

Kouhalvandi L, Aygun S, Ozdemir GG, Gunes EO. 10-bit High-speed CMOS comparator with offset cancellation technique. In Romanovs A, Navakauskas D, Senfelds A, editörler, Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 1-4. (Proceedings of the 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2017). doi: 10.1109/AIEEE.2017.8270524

10-bit High-speed CMOS comparator with offset cancellation technique

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