WOLA FFT Tabanli Kanallastirici Tasarimi

Translated title of the contribution: Design of WOLA FFT based channelizer

Enes Karav, Murvet Kirci, Oguzhan Kosar

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Citation (Scopus)

Abstract

The channelizer techniques that are common in use are examined in this thesis and weight overlap and add(WOLA) channelizer technique is designed in the MAT LAB Simulink platform and its advantages and disadvantages are examined in details. In the design phase, channelizer makes compatible for use with Xilinx FPGA family. VHSIC hardware identification language (VHDL) code of the channelizer that was designed on MATLAB Simulink is developed and synthesized on the Xilinx ISE platform. So, the resource utilization of the channelizer that was designed in the FPGA can be calculated.

Translated title of the contributionDesign of WOLA FFT based channelizer
Original languageTurkish
Title of host publication26th IEEE Signal Processing and Communications Applications Conference, SIU 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538615010
DOIs
Publication statusPublished - 5 Jul 2018
Event26th IEEE Signal Processing and Communications Applications Conference, SIU 2018 - Izmir, Turkey
Duration: 2 May 20185 May 2018

Publication series

Name26th IEEE Signal Processing and Communications Applications Conference, SIU 2018

Conference

Conference26th IEEE Signal Processing and Communications Applications Conference, SIU 2018
Country/TerritoryTurkey
CityIzmir
Period2/05/185/05/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

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