Abstract
The channelizer techniques that are common in use are examined in this thesis and weight overlap and add(WOLA) channelizer technique is designed in the MAT LAB Simulink platform and its advantages and disadvantages are examined in details. In the design phase, channelizer makes compatible for use with Xilinx FPGA family. VHSIC hardware identification language (VHDL) code of the channelizer that was designed on MATLAB Simulink is developed and synthesized on the Xilinx ISE platform. So, the resource utilization of the channelizer that was designed in the FPGA can be calculated.
Translated title of the contribution | Design of WOLA FFT based channelizer |
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Original language | Turkish |
Title of host publication | 26th IEEE Signal Processing and Communications Applications Conference, SIU 2018 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1-4 |
Number of pages | 4 |
ISBN (Electronic) | 9781538615010 |
DOIs | |
Publication status | Published - 5 Jul 2018 |
Event | 26th IEEE Signal Processing and Communications Applications Conference, SIU 2018 - Izmir, Turkey Duration: 2 May 2018 → 5 May 2018 |
Publication series
Name | 26th IEEE Signal Processing and Communications Applications Conference, SIU 2018 |
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Conference
Conference | 26th IEEE Signal Processing and Communications Applications Conference, SIU 2018 |
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Country/Territory | Turkey |
City | Izmir |
Period | 2/05/18 → 5/05/18 |
Bibliographical note
Publisher Copyright:© 2018 IEEE.