Abstract
A non-autonomous chaotic circuit which is suitable for high-frequency integrated circuit (IC) realization is presented. Simulation and experimental results verifying the feasibility of the circuit are given. We have numerically verified that the bit streams obtained from the stroboscopic Poincaré map of the system passed the four basic tests of FIPS-140-2 test suite. We also have verified that the binary data obtained from the hardware realization of this continuous-time chaotic oscillator in the same way pass the full NIST random number test suite. Then, in order to increase the output throughput and the statistical quality of the generated bit sequences, we propose a TRNG design which uses a dual oscillator architecture with the proposed continuous-time chaotic oscillator. Finally, we have experimentally verified that the binary data obtained by this oscillator sampling technique pass the tests of full NIST random number test suite without Von Neumann processing for a higher throughput speed while compared with the previous one where the proposed continuous-time chaotic oscillator is used alone.
Original language | English |
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Pages (from-to) | 235-242 |
Number of pages | 8 |
Journal | AEU - International Journal of Electronics and Communications |
Volume | 61 |
Issue number | 4 |
DOIs | |
Publication status | Published - 2 Apr 2007 |
Keywords
- Chaotic oscillators
- Random number generators