Abstract
Modeling the dynamic behavior of quadrotors with high accuracy is of great importance for controller and estimator design and realistic simulations of the whole system. A problem encountered here is in software-based simulations, which are generally used, when the accuracy of the system model increases, the simulation speed decreases considerably. In other words, there is a trade-off between simulation speed and system dynamics accuracy. To enhance this trade-off, system dynamics can be implemented based on hardware using FPGAs. Hardware-based simulation capability provides high speed and high accuracy. In this paper, transformation matrices in the 6-DoF mathematical model used to calculate the positions and orientations of quadrotors are targeted for hardware-based implementation. In simulations, it is aimed to design a hardware block that calculates the transformation matrix for the given Euler angles in a shorter time according to the software-based implementation. In this design, Taylor series expansion with the quarter-wave symmetry and Newton-Raphson division algorithm methods are chosen as the trigonometric function approximation. The fixed-point number representation method is chosen for FPGA implementation. After determining the dynamic range of the design, fixed-point word and fraction lengths are determined according to the DSP blocks and quarter-wave symmetry requirements on the FPGAs. Then, the system is designed using a Simulink environment, which consists of a datapath that uses the limited hardware resources on the FPGA and a state machine that controls this datapath. While designing the datapath as less as possible multipliers/adders are used. Finally, the system, whose accuracy is tested in the Simulink environment, is synthesized in Verilog language with automatic code generation method. In this article, a transformation matrix calculator needed in 6-DoF equations is designed using a hardware-based controller/datapath implementation that runs faster than a software-based implementation and consumes less resource on the FPGA.
Original language | English |
---|---|
Title of host publication | AIAA SciTech Forum and Exposition, 2023 |
Publisher | American Institute of Aeronautics and Astronautics Inc, AIAA |
ISBN (Print) | 9781624106996 |
DOIs | |
Publication status | Published - 2023 |
Event | AIAA SciTech Forum and Exposition, 2023 - Orlando, United States Duration: 23 Jan 2023 → 27 Jan 2023 |
Publication series
Name | AIAA SciTech Forum and Exposition, 2023 |
---|
Conference
Conference | AIAA SciTech Forum and Exposition, 2023 |
---|---|
Country/Territory | United States |
City | Orlando |
Period | 23/01/23 → 27/01/23 |
Bibliographical note
Publisher Copyright:© 2023, American Institute of Aeronautics and Astronautics Inc, AIAA. All rights reserved.