Abstract
We propose a novel hybrid bit parallel-serial processing technique called TALIPOT in order to reduce energy consumption of deep neural networks (DNNs). TALIPOT works as computation booster and has inborn ability of quality adjusting tradeoff between accuracy and energy consumption of DNNs. The core principal of TALIPOT is keeping the serial number of bits same in the entire computing process, so the energy is consumed effectively without extra waiting times between inputs and outputs of the computing blocks (adders, multipliers, and activation blocks). To achieve this, we implement activation rounding which scales down the accumulation of parallel bits at the output of the hidden layers of DNN. TALIPOT utilizes most significant bit first (MSB-first) fashion, so we obtain the most valuable bit information first, between the layers of DNN, which ensures the activation rounding process done accurately and efficiently. Thanks to this method, we optimize operating accuracy/energy point by cutting off bits at the output whenever we obtain the desired accuracy. Simulations using the MNIST and CIFAR-10 datasets show that TALIPOT outperforms the state-of-the-art computation techniques in terms of energy consumption. TALIPOT performs the MNIST classification with the energy efficiency of 25.3 TOPS/W and the accuracy of 98.2% in ASIC environment using 40 nm CMOS process.
Original language | English |
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Pages (from-to) | 2714-2727 |
Number of pages | 14 |
Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Volume | 41 |
Issue number | 8 |
DOIs | |
Publication status | Published - 1 Aug 2022 |
Bibliographical note
Publisher Copyright:© 1982-2012 IEEE.
Keywords
- Activation rounding
- ASIC
- deep neural network (DNN)
- hardware accelerator
- hybrid number representation (HNR)