Synthesis and Optimization of Switching Nanoarrays

Muhammed Ceylan Morgul; Mustafa Altun

doi:10.1109/DDECS.2015.51

Synthesis and Optimization of Switching Nanoarrays

Muhammed Ceylan Morgul, Mustafa Altun

Department of Electronics and Communication Engineering

Istanbul Technical University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Citations (Scopus)

Abstract

In this paper, we study implementation of Boolean functions with crossbar nanoarrays where each cross point behaves as a switch. This study has two main parts 'formulation' and 'optimization'. In the first part of formulation, we investigate Nan array based implementation methodologies in the literature. We classify them as two-terminal or four-terminal switch based. We generalize these methodologies to be applicable for any given Boolean function by offering array size formulations. In the second part of optimization, we focus on four-terminal switch based implementations, we propose a synthesis method to implement Boolean functions with optimal array sizes. Finally, we perform synthesis trials on standard benchmark circuits to evaluate the proposed optimal method in comparison with previous nanoarray based implementation methods. The proposed synthesis method gives by far the smallest array sizes and offers a new design paradigm for nanoarray based computing architectures.

Original language	English
Title of host publication	Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015
Editors	Heinrich Theodor Vierhaus, Zoran Stamenkovic, Witold Pleskacz, Jaan Raik
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	161-164
Number of pages	4
ISBN (Electronic)	9781479967803
DOIs	https://doi.org/10.1109/DDECS.2015.51
Publication status	Published - 13 Aug 2015
Event	18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015 - Belgrade, Serbia Duration: 22 Apr 2015 → 24 Apr 2015

Publication series

Name	Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015

Conference

Conference	18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015
Country/Territory	Serbia
City	Belgrade
Period	22/04/15 → 24/04/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

logic synthesis
optimization
switching nanoarrays

Access to Document

10.1109/DDECS.2015.51

Cite this

Morgul, M. C., & Altun, M. (2015). Synthesis and Optimization of Switching Nanoarrays. In H. T. Vierhaus, Z. Stamenkovic, W. Pleskacz, & J. Raik (Eds.), Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015 (pp. 161-164). Article 7195691 (Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DDECS.2015.51

Morgul, Muhammed Ceylan ; Altun, Mustafa. / Synthesis and Optimization of Switching Nanoarrays. Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015. editor / Heinrich Theodor Vierhaus ; Zoran Stamenkovic ; Witold Pleskacz ; Jaan Raik. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 161-164 (Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015).

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abstract = "In this paper, we study implementation of Boolean functions with crossbar nanoarrays where each cross point behaves as a switch. This study has two main parts 'formulation' and 'optimization'. In the first part of formulation, we investigate Nan array based implementation methodologies in the literature. We classify them as two-terminal or four-terminal switch based. We generalize these methodologies to be applicable for any given Boolean function by offering array size formulations. In the second part of optimization, we focus on four-terminal switch based implementations, we propose a synthesis method to implement Boolean functions with optimal array sizes. Finally, we perform synthesis trials on standard benchmark circuits to evaluate the proposed optimal method in comparison with previous nanoarray based implementation methods. The proposed synthesis method gives by far the smallest array sizes and offers a new design paradigm for nanoarray based computing architectures.",

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Morgul, MC & Altun, M 2015, Synthesis and Optimization of Switching Nanoarrays. in HT Vierhaus, Z Stamenkovic, W Pleskacz & J Raik (eds), Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015., 7195691, Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015, Institute of Electrical and Electronics Engineers Inc., pp. 161-164, 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015, Belgrade, Serbia, 22/04/15. https://doi.org/10.1109/DDECS.2015.51

Synthesis and Optimization of Switching Nanoarrays. / Morgul, Muhammed Ceylan; Altun, Mustafa.
Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015. ed. / Heinrich Theodor Vierhaus; Zoran Stamenkovic; Witold Pleskacz; Jaan Raik. Institute of Electrical and Electronics Engineers Inc., 2015. p. 161-164 7195691 (Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, we study implementation of Boolean functions with crossbar nanoarrays where each cross point behaves as a switch. This study has two main parts 'formulation' and 'optimization'. In the first part of formulation, we investigate Nan array based implementation methodologies in the literature. We classify them as two-terminal or four-terminal switch based. We generalize these methodologies to be applicable for any given Boolean function by offering array size formulations. In the second part of optimization, we focus on four-terminal switch based implementations, we propose a synthesis method to implement Boolean functions with optimal array sizes. Finally, we perform synthesis trials on standard benchmark circuits to evaluate the proposed optimal method in comparison with previous nanoarray based implementation methods. The proposed synthesis method gives by far the smallest array sizes and offers a new design paradigm for nanoarray based computing architectures.

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Morgul MC, Altun M. Synthesis and Optimization of Switching Nanoarrays. In Vierhaus HT, Stamenkovic Z, Pleskacz W, Raik J, editors, Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 161-164. 7195691. (Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015). doi: 10.1109/DDECS.2015.51

Synthesis and Optimization of Switching Nanoarrays

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