Synthesis and fundamental energy analysis of fault-tolerant CMOS circuits

Iike Ercan; Omercan Susam; Mustafa Altun; M. Husrev Cilasun

doi:10.1109/SMACD.2017.7981586

Synthesis and fundamental energy analysis of fault-tolerant CMOS circuits

Iike Ercan, Omercan Susam, Mustafa Altun, M. Husrev Cilasun

Department of Electronics and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

In this study, we perform a physical-information-theoretic analysis to obtain fundamental energy dissipation bounds for fault-tolerant reversible CMOS circuits we synthesize using Hamming codes. We show that the approach we had initially developed to calculate theoretical efficiency limitations of emerging electronic paradigms can also be applied to CMOS technology base and can provide feedback to improve circuit design and performance. We illustrate our physical-information-theoretic methodology via applications to circuits that we synthesized using Hamming codes that result in detection of up to (d-1) bit errors and correction of up to (d-1)/2 bit errors where d represents the minimum Hamming distance between any pair of bit patterns. The fundamental lower bounds on energy dissipation are calculated for a one-bit reversible full adder and for irreversible full adders with block-code-, dual modular redundancy (DMR)- and triple modular redundancy (TMR)-based CMOS circuits. Our results reflect the fundamental difference in energy limitations across these circuits and provide insights into improved design strategies.

Original language	English
Title of host publication	SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509050529
DOIs	https://doi.org/10.1109/SMACD.2017.7981586
Publication status	Published - 14 Jul 2017
Event	14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017 - Giardini Naxos, Taormina, Italy Duration: 12 Jun 2017 → 15 Jun 2017

Publication series

Name	SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design

Conference

Conference	14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017
Country/Territory	Italy
City	Giardini Naxos, Taormina
Period	12/06/17 → 15/06/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Keywords

error detection and correction
fault tolerance
Fundamental energy bounds
reversible circuits

Access to Document

10.1109/SMACD.2017.7981586

Cite this

Ercan, I., Susam, O., Altun, M., & Cilasun, M. H. (2017). Synthesis and fundamental energy analysis of fault-tolerant CMOS circuits. In SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design Article 7981586 (SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SMACD.2017.7981586

Ercan, Iike ; Susam, Omercan ; Altun, Mustafa et al. / Synthesis and fundamental energy analysis of fault-tolerant CMOS circuits. SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Institute of Electrical and Electronics Engineers Inc., 2017. (SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design).

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Ercan, I, Susam, O, Altun, M & Cilasun, MH 2017, Synthesis and fundamental energy analysis of fault-tolerant CMOS circuits. in SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design., 7981586, SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Institute of Electrical and Electronics Engineers Inc., 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017, Giardini Naxos, Taormina, Italy, 12/06/17. https://doi.org/10.1109/SMACD.2017.7981586

Synthesis and fundamental energy analysis of fault-tolerant CMOS circuits. / Ercan, Iike; Susam, Omercan; Altun, Mustafa et al.
SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Institute of Electrical and Electronics Engineers Inc., 2017. 7981586 (SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Susam, Omercan

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N2 - In this study, we perform a physical-information-theoretic analysis to obtain fundamental energy dissipation bounds for fault-tolerant reversible CMOS circuits we synthesize using Hamming codes. We show that the approach we had initially developed to calculate theoretical efficiency limitations of emerging electronic paradigms can also be applied to CMOS technology base and can provide feedback to improve circuit design and performance. We illustrate our physical-information-theoretic methodology via applications to circuits that we synthesized using Hamming codes that result in detection of up to (d-1) bit errors and correction of up to (d-1)/2 bit errors where d represents the minimum Hamming distance between any pair of bit patterns. The fundamental lower bounds on energy dissipation are calculated for a one-bit reversible full adder and for irreversible full adders with block-code-, dual modular redundancy (DMR)- and triple modular redundancy (TMR)-based CMOS circuits. Our results reflect the fundamental difference in energy limitations across these circuits and provide insights into improved design strategies.

AB - In this study, we perform a physical-information-theoretic analysis to obtain fundamental energy dissipation bounds for fault-tolerant reversible CMOS circuits we synthesize using Hamming codes. We show that the approach we had initially developed to calculate theoretical efficiency limitations of emerging electronic paradigms can also be applied to CMOS technology base and can provide feedback to improve circuit design and performance. We illustrate our physical-information-theoretic methodology via applications to circuits that we synthesized using Hamming codes that result in detection of up to (d-1) bit errors and correction of up to (d-1)/2 bit errors where d represents the minimum Hamming distance between any pair of bit patterns. The fundamental lower bounds on energy dissipation are calculated for a one-bit reversible full adder and for irreversible full adders with block-code-, dual modular redundancy (DMR)- and triple modular redundancy (TMR)-based CMOS circuits. Our results reflect the fundamental difference in energy limitations across these circuits and provide insights into improved design strategies.

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Ercan I, Susam O, Altun M, Cilasun MH. Synthesis and fundamental energy analysis of fault-tolerant CMOS circuits. In SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Institute of Electrical and Electronics Engineers Inc. 2017. 7981586. (SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design). doi: 10.1109/SMACD.2017.7981586

Synthesis and fundamental energy analysis of fault-tolerant CMOS circuits

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