Abstract
This paper presents a reliability simulation framework based on surrogate modeling. A novel methodology has been developed, which integrates variability analysis with the reliability concepts by employing transistor drain-current surrogate models in terms of crucial process parameters, bias voltages, temperature, and time. Simulation techniques using these models enables exploration of the effects of time-based degradation on analog circuits. The analysis of a differential amplifier at the 65-nm technology node reveals that the dc current is reduced by around 10% in ten years. The tool is used to demonstrate how the biasing structures of analog circuits can be designed to boost aging resilience.
| Original language | English |
|---|---|
| Article number | 5893925 |
| Pages (from-to) | 458-465 |
| Number of pages | 8 |
| Journal | IEEE Transactions on Device and Materials Reliability |
| Volume | 11 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - Sept 2011 |
| Externally published | Yes |
Keywords
- Aging analysis
- analog circuits
- process variations
- reliability
- surrogate model
- time-based degradation
- variability