Seri Çevresel Arayüzü için Evrensel Doʇrulama Metodu ile Test Ortaminin Oluşturulmasi

Buse Ustaoglu; Ahmet Cagri Bagbaba; Berna Ors; Inan Erdem

doi:10.1109/SIU.2015.7130358

Seri Çevresel Arayüzü için Evrensel Doʇrulama Metodu ile Test Ortaminin Oluşturulmasi

Translated title of the contribution: Creating test environment with UVM for SPI

Buse Ustaoglu, Ahmet Cagri Bagbaba, Berna Ors, Inan Erdem

Department of Electronics and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

In order to implement reliable digital system, it is becoming important making tests and finding bugs by setting up a verification environment. It is possible to set up effective verification environment by using Universal Verification Methodology which is standardized and used in worldwide chip industry. In this work, the slave circuit of Serial Peripheral Interface, which is commonly used for communication integrated circuits, have been designed with hardware description and verification language SystemVerilog and creating test environment with UVM.

Translated title of the contribution	Creating test environment with UVM for SPI
Original language	Turkish
Title of host publication	2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2373-2376
Number of pages	4
ISBN (Electronic)	9781467373869
DOIs	https://doi.org/10.1109/SIU.2015.7130358
Publication status	Published - 19 Jun 2015
Event	2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Malatya, Turkey Duration: 16 May 2015 → 19 May 2015

Publication series

Name	2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings

Conference

Conference	2015 23rd Signal Processing and Communications Applications Conference, SIU 2015
Country/Territory	Turkey
City	Malatya
Period	16/05/15 → 19/05/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Access to Document

10.1109/SIU.2015.7130358

Cite this

Ustaoglu, B., Bagbaba, A. C., Ors, B., & Erdem, I. (2015). Seri Çevresel Arayüzü için Evrensel Doʇrulama Metodu ile Test Ortaminin Oluşturulmasi. In 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings (pp. 2373-2376). Article 7130358 (2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SIU.2015.7130358

Ustaoglu, Buse ; Bagbaba, Ahmet Cagri ; Ors, Berna et al. / Seri Çevresel Arayüzü için Evrensel Doʇrulama Metodu ile Test Ortaminin Oluşturulmasi. 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 2373-2376 (2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings).

@inproceedings{bba24dbc242f4830b03cd5a37b1a9f1b,

title = "Seri {\c C}evresel Aray{\"u}z{\"u} i{\c c}in Evrensel Doʇrulama Metodu ile Test Ortaminin Olu{\c s}turulmasi",

abstract = "In order to implement reliable digital system, it is becoming important making tests and finding bugs by setting up a verification environment. It is possible to set up effective verification environment by using Universal Verification Methodology which is standardized and used in worldwide chip industry. In this work, the slave circuit of Serial Peripheral Interface, which is commonly used for communication integrated circuits, have been designed with hardware description and verification language SystemVerilog and creating test environment with UVM.",

keywords = "Serial peripheral interface(SPI), Simulation, Test, Universal verification methodology(UVM)",

author = "Buse Ustaoglu and Bagbaba, {Ahmet Cagri} and Berna Ors and Inan Erdem",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 ; Conference date: 16-05-2015 Through 19-05-2015",

year = "2015",

month = jun,

day = "19",

doi = "10.1109/SIU.2015.7130358",

language = "T{\"u}rk{\c c}e",

series = "2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "2373--2376",

booktitle = "2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings",

address = "United States",

}

Ustaoglu, B, Bagbaba, AC, Ors, B & Erdem, I 2015, Seri Çevresel Arayüzü için Evrensel Doʇrulama Metodu ile Test Ortaminin Oluşturulmasi. in 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings., 7130358, 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 2373-2376, 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015, Malatya, Turkey, 16/05/15. https://doi.org/10.1109/SIU.2015.7130358

Seri Çevresel Arayüzü için Evrensel Doʇrulama Metodu ile Test Ortaminin Oluşturulmasi. / Ustaoglu, Buse; Bagbaba, Ahmet Cagri; Ors, Berna et al.
2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. p. 2373-2376 7130358 (2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Seri Çevresel Arayüzü için Evrensel Doʇrulama Metodu ile Test Ortaminin Oluşturulmasi

AU - Ustaoglu, Buse

AU - Bagbaba, Ahmet Cagri

AU - Ors, Berna

AU - Erdem, Inan

PY - 2015/6/19

Y1 - 2015/6/19

N2 - In order to implement reliable digital system, it is becoming important making tests and finding bugs by setting up a verification environment. It is possible to set up effective verification environment by using Universal Verification Methodology which is standardized and used in worldwide chip industry. In this work, the slave circuit of Serial Peripheral Interface, which is commonly used for communication integrated circuits, have been designed with hardware description and verification language SystemVerilog and creating test environment with UVM.

AB - In order to implement reliable digital system, it is becoming important making tests and finding bugs by setting up a verification environment. It is possible to set up effective verification environment by using Universal Verification Methodology which is standardized and used in worldwide chip industry. In this work, the slave circuit of Serial Peripheral Interface, which is commonly used for communication integrated circuits, have been designed with hardware description and verification language SystemVerilog and creating test environment with UVM.

KW - Serial peripheral interface(SPI)

KW - Simulation

KW - Test

KW - Universal verification methodology(UVM)

UR - http://www.scopus.com/inward/record.url?scp=84939204934&partnerID=8YFLogxK

U2 - 10.1109/SIU.2015.7130358

DO - 10.1109/SIU.2015.7130358

M3 - Konferans katkısı

AN - SCOPUS:84939204934

T3 - 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings

SP - 2373

EP - 2376

BT - 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015

Y2 - 16 May 2015 through 19 May 2015

ER -

Ustaoglu B, Bagbaba AC, Ors B, Erdem I. Seri Çevresel Arayüzü için Evrensel Doʇrulama Metodu ile Test Ortaminin Oluşturulmasi. In 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2015. p. 2373-2376. 7130358. (2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings). doi: 10.1109/SIU.2015.7130358

Seri Çevresel Arayüzü için Evrensel Doʇrulama Metodu ile Test Ortaminin Oluşturulmasi

Abstract

Publication series

Conference

Bibliographical note

Access to Document

Other files and links

Fingerprint

Cite this