Abstract
In modern CMOS technology, local electrical stress has substantially increased as device geometries scaled down more aggressively compared to supply voltages. As a result, time-dependent degradation mechanisms (aging phenomena) became an important performance problem, which leads to a considerable lifetime reduction in manufactured integrated circuits. Combination of these aging phenomena with process variations has made reliability a major design objective. In analog circuits, different approaches have been proposed to mitigate the performance challenges related to device reliability. This paper discusses aging in CMOS technology and reviews reliability-aware analog circuit design methodologies for nanoscale circuits.
Original language | English |
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Title of host publication | SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781509050529 |
DOIs | |
Publication status | Published - 14 Jul 2017 |
Event | 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017 - Giardini Naxos, Taormina, Italy Duration: 12 Jun 2017 → 15 Jun 2017 |
Publication series
Name | SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design |
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Conference
Conference | 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017 |
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Country/Territory | Italy |
City | Giardini Naxos, Taormina |
Period | 12/06/17 → 15/06/17 |
Bibliographical note
Publisher Copyright:© 2017 IEEE.