Review: Analog design methodologies for reliability in nanoscale CMOS circuits

Engin Afacan, Mustafa Berke Yelten, Gunhan Dundar

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

20 Citations (Scopus)

Abstract

In modern CMOS technology, local electrical stress has substantially increased as device geometries scaled down more aggressively compared to supply voltages. As a result, time-dependent degradation mechanisms (aging phenomena) became an important performance problem, which leads to a considerable lifetime reduction in manufactured integrated circuits. Combination of these aging phenomena with process variations has made reliability a major design objective. In analog circuits, different approaches have been proposed to mitigate the performance challenges related to device reliability. This paper discusses aging in CMOS technology and reviews reliability-aware analog circuit design methodologies for nanoscale circuits.

Original languageEnglish
Title of host publicationSMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509050529
DOIs
Publication statusPublished - 14 Jul 2017
Event14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017 - Giardini Naxos, Taormina, Italy
Duration: 12 Jun 201715 Jun 2017

Publication series

NameSMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design

Conference

Conference14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017
Country/TerritoryItaly
CityGiardini Naxos, Taormina
Period12/06/1715/06/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

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