Abstract
A new response system is suggested to show the security vulnerabilities of an FPGA-based chaotic "true" random number generator (RNG). The auto-synchronization method is used to justify the success of the response system. The hidden parameter of the chaotic RNG is revealed when the design of the RNG is open to everyone and a limited scalar time series can be monitored from the chaotic RNG. Experimental results prove the applicability of the response system in a way of estimating next bit while the same bit stream of the RNG can be reproduced.
Original language | English |
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Title of host publication | 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781728133201 |
Publication status | Published - 2020 |
Externally published | Yes |
Event | 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online Duration: 10 Oct 2020 → 21 Oct 2020 |
Publication series
Name | Proceedings - IEEE International Symposium on Circuits and Systems |
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Volume | 2020-October |
ISSN (Print) | 0271-4310 |
Conference
Conference | 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 |
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City | Virtual, Online |
Period | 10/10/20 → 21/10/20 |
Bibliographical note
Publisher Copyright:© 2021 IEEE
Keywords
- Auto-synchronization
- FPGA
- Random number generator
- Security weaknesses