Reconvergent Path-aware Simulation of Bit-stream Processing

Sercan Aygun; M. Hassan Najafi; Mohsen Imani; Ece Olcay Gunes

doi:10.1145/3583781.3590323

Reconvergent Path-aware Simulation of Bit-stream Processing

Sercan Aygun, M. Hassan Najafi, Mohsen Imani, Ece Olcay Gunes

Department of Electronics and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Few studies have explored the complex circuit simulation of stochastic and unary computing systems, which are referred to under the umbrella term of bit-stream processing. The computer simulation of multi-level cascaded circuits with reconvergent paths has not been largely examined in the context of bit-stream processing systems. This study addresses this gap and proposes a contingency table -based reconvergent path-aware simulation method for fast and efficient simulation of multi-level circuits. The proposed method exhibits significantly better runtime and accuracy.

Original language	English
Title of host publication	GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023
Publisher	Association for Computing Machinery
Pages	225-226
Number of pages	2
ISBN (Electronic)	9798400701252
DOIs	https://doi.org/10.1145/3583781.3590323
Publication status	Published - 5 Jun 2023
Event	33rd Great Lakes Symposium on VLSI, GLSVLSI 2023 - Knoxville, United States Duration: 5 Jun 2023 → 7 Jun 2023

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference	33rd Great Lakes Symposium on VLSI, GLSVLSI 2023
Country/Territory	United States
City	Knoxville
Period	5/06/23 → 7/06/23

Bibliographical note

Publisher Copyright:
© 2023 Owner/Author.

Funding

This work was supported in part by National Science Foundation (NSF) grants #2127780 and #2019511, Semiconductor Research Corporation (SRC), O ce of Naval Research, grant #N00014-21-1-2225 and #N00014-22-1-2067, the Air Force O ce of Scientific Research under award #FA9550-22-1-0253, the Louisiana Board of Regents Support Fund #LEQSF(2020-23)-RD-A-26, and generous gifts from Cisco, Xilinx, and Nvidia. This work was supported in part by National Science Foundation (NSF) grants #2127780 and #2019511, Semiconductor Research Corporation (SRC), Office of Naval Research, grant #N00014-21-1-2225 and #N00014-22-1-2067, the Air Force Office of Scientific Research under award #FA9550-22-1-0253, the Louisiana Board of Regents Support Fund #LEQSF(2020-23)-RD-A-26, and generous gifts from Cisco, Xilinx, and Nvidia.

Funders	Funder number
Air Force O ce of Scientific Research
O ce of Naval Research
National Science Foundation	2019511, 2127780
Office of Naval Research	00014-21-1-2225, 00014-22-1-2067
Semiconductor Research Corporation
Air Force Office of Scientific Research	9550-22-1-0253
Louisiana Board of Regents	2020-23)-RD-A-26

Keywords

bit-stream processing
reconvergence
simulation

Access to Document

10.1145/3583781.3590323

Cite this

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title = "Reconvergent Path-aware Simulation of Bit-stream Processing",

abstract = "Few studies have explored the complex circuit simulation of stochastic and unary computing systems, which are referred to under the umbrella term of bit-stream processing. The computer simulation of multi-level cascaded circuits with reconvergent paths has not been largely examined in the context of bit-stream processing systems. This study addresses this gap and proposes a contingency table -based reconvergent path-aware simulation method for fast and efficient simulation of multi-level circuits. The proposed method exhibits significantly better runtime and accuracy.",

keywords = "bit-stream processing, reconvergence, simulation",

author = "Sercan Aygun and Najafi, {M. Hassan} and Mohsen Imani and Gunes, {Ece Olcay}",

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doi = "10.1145/3583781.3590323",

language = "English",

series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

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Aygun, S, Najafi, MH, Imani, M & Gunes, EO 2023, Reconvergent Path-aware Simulation of Bit-stream Processing. in GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, Association for Computing Machinery, pp. 225-226, 33rd Great Lakes Symposium on VLSI, GLSVLSI 2023, Knoxville, United States, 5/06/23. https://doi.org/10.1145/3583781.3590323

Reconvergent Path-aware Simulation of Bit-stream Processing. / Aygun, Sercan; Najafi, M. Hassan; Imani, Mohsen et al.
GLSVLSI 2023 - Proceedings of the Great Lakes Symposium on VLSI 2023. Association for Computing Machinery, 2023. p. 225-226 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Few studies have explored the complex circuit simulation of stochastic and unary computing systems, which are referred to under the umbrella term of bit-stream processing. The computer simulation of multi-level cascaded circuits with reconvergent paths has not been largely examined in the context of bit-stream processing systems. This study addresses this gap and proposes a contingency table -based reconvergent path-aware simulation method for fast and efficient simulation of multi-level circuits. The proposed method exhibits significantly better runtime and accuracy.

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Reconvergent Path-aware Simulation of Bit-stream Processing

Abstract

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Keywords

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