## Abstract

Switching lattices, consisting of four-terminal switches, present an alternative structure for the realization of Boolean logic functions. Although promising algorithms have been introduced to find a realization of a logic function using a switching lattice with the fewest number of four-terminal switches, the delay of a switching lattice has not been examined yet. In this article, we generate a switching lattice using a recently proposed CMOS-compatible four-terminal device model and formulate the delay of a path in a switching lattice. It is observed that the delay of a design realizing a logic function on a switching lattice heavily depends on the number of four-terminal switches in the critical path. With this motivation, we introduce optimization algorithms, called PHAEDRA and TROADES, which can find the realization of a logic function on a switching lattice with the fewest number of switches under a delay constraint given in terms of the number of switches in the critical path. While PHAEDRA is a dichotomic search algorithm that can obtain solutions with a small number of switches on small size logic functions, TROADES is a divide-and-conquer method that can find a solution using less computational effort and can easily handle larger size logic functions with respect to PHAEDRA. The experimental results show that the proposed algorithms can reduce the delay of a lattice realization of a logic function significantly at a cost of an increase in the number of switches. They can explore alternative lattice realizations of a logic function by changing the delay constraint, enabling a designer to choose the one that fits best in an application.

Original language | English |
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Pages (from-to) | 2036-2048 |

Number of pages | 13 |

Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |

Volume | 40 |

Issue number | 10 |

DOIs | |

Publication status | Published - Oct 2021 |

Externally published | Yes |

### Bibliographical note

Publisher Copyright:© 1982-2012 IEEE.

### Funding

Manuscript received March 4, 2020; revised May 27, 2020 and August 27, 2020; accepted October 29, 2020. Date of publication November 3, 2020; date of current version September 20, 2021. This work was supported in part by the TUBITAK-Career Project under Grant 113E760, and in part by the TUBITAK-2501 Project under Grant 218E068. This article was recommended by Associate Editor S. X. Hu. (Corresponding author: Nihat Akkan.) Levent Aksoy and Mustafa Altun are with the Emerging Circuits and Computation Group, Department of Electronics and Communication Engineering, Istanbul Technical University, 34469 Istanbul, Turkey (e-mail: [email protected]; [email protected]).

Funders | Funder number |
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TUBITAK-2501 | 218E068 |

## Keywords

- Binary search
- divide and conquer
- Elmore delay
- emerging technologies
- four-terminal switch
- logic synthesis
- satisfiability (SAT)
- switching lattice