TY - GEN
T1 - Power-delay-area performance modeling and analysis for nano-crossbar arrays
AU - Morgul, Muhammed Ceylan
AU - Peker, Furkan
AU - Altun, Mustafa
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/9/2
Y1 - 2016/9/2
N2 - In this study, we introduce an accurate capacitor-resistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. Although the proposed model is technology independent, we explicitly show its applicability for three different nanoarray technologies where each crosspoint behaves as a diode, a FET, and a four-terminal switch. In order to find related capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies. Comparison between the proposed model and a conventional simple one, which generally uses one/two capacitors for each crosspoint, demonstrates the necessity of using our model in order to accurately calculate power and delay values. The only exception where both models give approximately same results is the presence of considerably low valued resistive connections between switches. However, we show that this is a rare case for nano-crossbar technologies.
AB - In this study, we introduce an accurate capacitor-resistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. Although the proposed model is technology independent, we explicitly show its applicability for three different nanoarray technologies where each crosspoint behaves as a diode, a FET, and a four-terminal switch. In order to find related capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies. Comparison between the proposed model and a conventional simple one, which generally uses one/two capacitors for each crosspoint, demonstrates the necessity of using our model in order to accurately calculate power and delay values. The only exception where both models give approximately same results is the presence of considerably low valued resistive connections between switches. However, we show that this is a rare case for nano-crossbar technologies.
KW - circuit modeling
KW - emerging technologies
KW - Nano-crossbar array
KW - performance analysis
KW - post-CMOS
UR - http://www.scopus.com/inward/record.url?scp=84988960154&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2016.100
DO - 10.1109/ISVLSI.2016.100
M3 - Conference contribution
AN - SCOPUS:84988960154
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 437
EP - 442
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
PB - IEEE Computer Society
T2 - 15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
Y2 - 11 July 2016 through 13 July 2016
ER -