Power-delay-area performance modeling and analysis for nano-crossbar arrays

Muhammed Ceylan Morgul, Furkan Peker, Mustafa Altun

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Citations (Scopus)

Abstract

In this study, we introduce an accurate capacitor-resistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. Although the proposed model is technology independent, we explicitly show its applicability for three different nanoarray technologies where each crosspoint behaves as a diode, a FET, and a four-terminal switch. In order to find related capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies. Comparison between the proposed model and a conventional simple one, which generally uses one/two capacitors for each crosspoint, demonstrates the necessity of using our model in order to accurately calculate power and delay values. The only exception where both models give approximately same results is the presence of considerably low valued resistive connections between switches. However, we show that this is a rare case for nano-crossbar technologies.

Original languageEnglish
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
PublisherIEEE Computer Society
Pages437-442
Number of pages6
ISBN (Electronic)9781467390385
DOIs
Publication statusPublished - 2 Sept 2016
Event15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016 - Pittsburgh, United States
Duration: 11 Jul 201613 Jul 2016

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2016-September
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Conference

Conference15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
Country/TerritoryUnited States
CityPittsburgh
Period11/07/1613/07/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Funding

FundersFunder number
Horizon 2020 Framework Programme691178

    Keywords

    • circuit modeling
    • emerging technologies
    • Nano-crossbar array
    • performance analysis
    • post-CMOS

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