Power analysis resistant hardware implementations of AES

Levent Ordu*, Berna Örs

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Citations (Scopus)

Abstract

This paper presents the first FPGA implementation of the Advanced Encryption Standard (AES) with masking countermeasure for the power analysis (PA) attacks. PA is a powerful side-channel analysis (SCA) attack. A side-channel analysis (SCA) attack takes advantage of implementation specific characteristics to recover the secret parameters involved in the computation. The goals of side-channel attack countermeasures are reducing the correlation between the side-channel data and the secret data. Data masking is one of the most powerful countermeasure against side channel attacks. The message and the key are masked with some random values at the beginning of computations. We have implemented the AES algorithm on an FPGA by using two different masking method: multiplicative and additive.

Original languageEnglish
Title of host publicationICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
Pages1408-1411
Number of pages4
DOIs
Publication statusPublished - 2007
Event14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco
Duration: 11 Dec 200714 Dec 2007

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

Conference14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
Country/TerritoryMorocco
CityMarrakech
Period11/12/0714/12/07

Keywords

  • AES
  • Masking
  • Power analysis attacks

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